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fix(boards): Move ARM clock config to DTS.

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This commit is contained in:
Peter Johanson 2022-02-21 23:26:34 -05:00 committed by Pete Johanson
parent 9203ae217b
commit cc51562f78
8 changed files with 122 additions and 66 deletions
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23
app/boards/arm/bdn9/bdn9_rev2.dts
View file

@ -6,6 +6,7 @@
/dts-v1/;
#include <st/f0/stm32f072Xb.dtsi>
#include <st/f0/stm32f072c(8-b)tx-pinctrl.dtsi>
#include <dt-bindings/led/led.h>
/ {
@ -82,8 +83,28 @@
};
};
&clk_hsi {
status = "okay";
};
&pll {
status = "okay";
prediv = <1>;
mul = <6>;
clocks = <&clk_hsi>;
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
&usb {
status = "okay";
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
cdc_acm_uart: cdc_acm_uart {
compatible = "zephyr,cdc-acm-uart";
label = "CDC_ACM_0";
@ -105,7 +126,7 @@
#size-cells = <1>;
/* Set 6Kb of storage at the end of the 128Kb of flash */
storage_partition: partition@3e800 {
storage_partition: partition@1e800 {
label = "storage";
reg = <0x0001e800 0x00001800>;
};

18
app/boards/arm/bdn9/bdn9_rev2_defconfig
View file

@ -11,11 +11,11 @@ CONFIG_FPU=y
# enable GPIO
CONFIG_GPIO=y
# Needed for matrix to properly work
CONFIG_ZMK_KSCAN_DIRECT_POLLING=y
# Enable pinctrl
CONFIG_PINCTRL=y
# Enable pinmux
CONFIG_PINMUX=y
# Poll to avoid interrupt overlap issues
CONFIG_ZMK_KSCAN_DIRECT_POLLING=y
# Needed to reduce this to size that will fit on F072
CONFIG_HEAP_MEM_POOL_SIZE=1024
@ -23,13 +23,3 @@ CONFIG_HEAP_MEM_POOL_SIZE=1024
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSI as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_PREDIV=1
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=12
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1

20
app/boards/arm/ferris/ferris_rev02.dts
View file

@ -99,6 +99,7 @@
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
@ -117,6 +118,25 @@
status = "okay";
};
&clk_hsi {
status = "okay";
};
&pll {
prediv = <1>;
mul = <6>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
&rtc {
status = "okay";
cdc_acm_uart: cdc_acm_uart {

12
app/boards/arm/ferris/ferris_rev02_defconfig
View file

@ -7,7 +7,7 @@ CONFIG_SOC_STM32F072XB=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
# enable PINMUX
CONFIG_PINMUX=y
CONFIG_PINCTRL=y
# enable GPIO
CONFIG_GPIO=y
@ -31,13 +31,3 @@ CONFIG_HEAP_MEM_POOL_SIZE=1024
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSI as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
# produce 48MHz clock at PLL output
# CONFIG_CLOCK_STM32_PLL_PREDIV=1
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=6
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=1
# CONFIG_CLOCK_STM32_APB2_PRESCALER=1

25
app/boards/arm/planck/planck_rev6.dts
View file

@ -1,11 +1,12 @@
/*
* Copyright (c) 2017 I-SENSE group of ICCS
* Copyright (c) 2020 The ZMK Contributors
*
* SPDX-License-Identifier: MIT
*/
/dts-v1/;
#include <st/f3/stm32f303Xc.dtsi>
#include <st/f3/stm32f303c(b-c)tx-pinctrl.dtsi>
#include <dt-bindings/zmk/matrix_transform.h>
/ {
@ -83,6 +84,8 @@ layout_2x2u_transform:
};
&usb {
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
status = "okay";
cdc_acm_uart: cdc_acm_uart {
compatible = "zephyr,cdc-acm-uart";
@ -90,6 +93,26 @@ layout_2x2u_transform:
};
};
&clk_hse {
status = "okay";
clock-frequency = <DT_FREQ_M(8)>;
};
&pll {
prediv = <1>;
mul = <9>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(72)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&flash0 {
/*
* For more information, see:

13
app/boards/arm/planck/planck_rev6_defconfig
View file

@ -8,21 +8,10 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# enable pinmux
CONFIG_PINMUX=y
CONFIG_PINCTRL=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_PREDIV=1
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1

36
app/boards/arm/proton_c/proton_c.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 Pete Johanson
* Copyright (c) 2020 The ZMK Contributors
*
* SPDX-License-Identifier: MIT
*/
@ -16,6 +16,11 @@
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &cdc_acm_uart0;
};
aliases {
led0 = &led;
};
leds {
@ -29,18 +34,47 @@
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
};
&spi2 {
pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
};
&clk_hse {
status = "okay";
clock-frequency = <DT_FREQ_M(8)>;
};
&pll {
prediv = <1>;
mul = <9>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(72)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&usb {
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
status = "okay";
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
label = "CDC_ACM_0";
};
};
&rtc {

15
app/boards/arm/proton_c/proton_c_defconfig
View file

@ -8,8 +8,8 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# Floating Point Options
CONFIG_FPU=y
# enable pinmux
CONFIG_PINMUX=y
# enable pinctrl
CONFIG_PINCTRL=y
# enable GPIO
CONFIG_GPIO=y
@ -17,14 +17,3 @@ CONFIG_GPIO=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_PREDIV=1
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1