35e73d40f5
* BDN9 Rev2 requires direct polling, interrupts don't work as expected.
35 lines
813 B
Text
35 lines
813 B
Text
# SPDX-License-Identifier: MIT
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CONFIG_SOC_SERIES_STM32F0X=y
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CONFIG_SOC_STM32F072XB=y
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# 72MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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# Floating Point Options
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CONFIG_FPU=y
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# enable GPIO
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CONFIG_GPIO=y
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# Needed for matrix to properly work
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CONFIG_ZMK_KSCAN_DIRECT_POLLING=y
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# Enable pinmux
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CONFIG_PINMUX=y
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# Needed to reduce this to size that will fit on F072
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CONFIG_HEAP_MEM_POOL_SIZE=1024
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# clock configuration
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CONFIG_CLOCK_CONTROL=y
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# Clock configuration for Cube Clock control driver
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# use HSI as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_PREDIV=1
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CONFIG_CLOCK_STM32_PLL_MULTIPLIER=12
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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