feat(gpio): Add 595 shift register driver.
* Use SPI for sending serial data. * Supports 1-4 shift registers chained together by setting `ngios` property appropriately.
This commit is contained in:
Peter Johanson
Pete Johanson
parent
8e67524e62
commit
6a86cd0547
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@ -4,5 +4,5 @@
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zephyr_library_named(zmk__drivers__gpio)
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zephyr_library_include_directories(${CMAKE_SOURCE_DIR}/include)
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zephyr_library_sources_ifdef(CONFIG_GPIO_595 gpio_595.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MCP23017 gpio_mcp23017.c)
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zephyr_library_sources_ifndef(CONFIG_GPIO_MCP23017 ${ZEPHYR_BASE}/misc/empty_file.c)
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@ -1 +1,2 @@
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rsource "Kconfig.mcp23017"
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rsource "Kconfig.595"
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@ -0,0 +1,24 @@
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# 595 GPIO configuration options
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# Copyright (c) 2022 The ZMK Contributors
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# SPDX-License-Identifier: MIT
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DT_COMPAT_ZMK_GPIO_595 := zmk,gpio-595
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menuconfig GPIO_595
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bool "595 Shift Register SPI driver"
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default $(dt_compat_enabled,$(DT_COMPAT_ZMK_GPIO_595))
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depends on SPI
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select HAS_DTS_GPIO
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help
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Enable driver for 595 shift register chip using SPI.
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if GPIO_595
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config GPIO_595_INIT_PRIORITY
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int "Init priority"
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default 75
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help
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Device driver initialization priority.
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endif #GPIO_595
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@ -0,0 +1,215 @@
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/*
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* Copyright (c) 2022 The ZMK Contributors
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*
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* SPDX-License-Identifier: MIT
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*/
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#define DT_DRV_COMPAT zmk_gpio_595
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/**
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* @file Driver for 595 SPI-based GPIO driver.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <sys/byteorder.h>
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#include <drivers/gpio.h>
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#include <drivers/spi.h>
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(gpio_595);
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/** Configuration data */
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struct reg_595_config {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_config common;
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struct spi_dt_spec bus;
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uint8_t ngpios;
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};
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/** Runtime driver data */
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struct reg_595_drv_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_config data;
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struct k_sem lock;
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uint32_t gpio_cache;
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};
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static int reg_595_write_registers(const struct device *dev, uint32_t value) {
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const struct reg_595_config *config = dev->config;
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struct reg_595_drv_data *const drv_data = (struct reg_595_drv_data *const)dev->data;
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int ret = 0;
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uint8_t nwrite = config->ngpios / 8;
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uint32_t reg_data = sys_cpu_to_be32(value);
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/* Allow a sequence of 1-4 registers in sequence, lowest byte is for the first in the chain */
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const struct spi_buf tx_buf[1] = {{
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.buf = ((uint8_t *)®_data) + (4 - nwrite),
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.len = nwrite,
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}};
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const struct spi_buf_set tx = {
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.buffers = tx_buf,
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.count = ARRAY_SIZE(tx_buf),
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};
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ret = spi_write_dt(&config->bus, &tx);
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if (ret < 0) {
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LOG_ERR("spi_write FAIL %d\n", ret);
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return ret;
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}
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drv_data->gpio_cache = value;
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return 0;
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}
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/**
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* @brief Setup the pin direction (input or output)
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*
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* @param dev Device struct of the 595
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int setup_pin_dir(const struct device *dev, uint32_t pin, int flags) {
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if ((flags & GPIO_OUTPUT) == 0U) {
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return -ENOTSUP;
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}
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return 0;
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}
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static int reg_595_pin_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) {
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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if ((flags & GPIO_OPEN_DRAIN) != 0U) {
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return -ENOTSUP;
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};
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ret = setup_pin_dir(dev, pin, flags);
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if (ret) {
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LOG_ERR("595: error setting pin direction (%d)", ret);
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}
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return ret;
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}
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static int reg_595_port_get_raw(const struct device *dev, uint32_t *value) { return -ENOTSUP; }
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static int reg_595_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value) {
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struct reg_595_drv_data *const drv_data = (struct reg_595_drv_data *const)dev->data;
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uint32_t buf;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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buf = drv_data->gpio_cache;
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buf = (buf & ~mask) | (mask & value);
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ret = reg_595_write_registers(dev, buf);
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static int reg_595_port_set_bits_raw(const struct device *dev, uint32_t mask) {
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return reg_595_port_set_masked_raw(dev, mask, mask);
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}
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static int reg_595_port_clear_bits_raw(const struct device *dev, uint32_t mask) {
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return reg_595_port_set_masked_raw(dev, mask, 0);
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}
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static int reg_595_port_toggle_bits(const struct device *dev, uint32_t mask) {
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struct reg_595_drv_data *const drv_data = (struct reg_595_drv_data *const)dev->data;
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uint32_t buf;
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int ret;
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/* Can't do SPI bus operations from an ISR */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_sem_take(&drv_data->lock, K_FOREVER);
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buf = drv_data->gpio_cache;
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buf ^= mask;
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ret = reg_595_write_registers(dev, buf);
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k_sem_give(&drv_data->lock);
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return ret;
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}
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static const struct gpio_driver_api api_table = {
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.pin_configure = reg_595_pin_config,
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.port_get_raw = reg_595_port_get_raw,
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.port_set_masked_raw = reg_595_port_set_masked_raw,
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.port_set_bits_raw = reg_595_port_set_bits_raw,
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.port_clear_bits_raw = reg_595_port_clear_bits_raw,
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.port_toggle_bits = reg_595_port_toggle_bits,
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};
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/**
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* @brief Initialization function of 595
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*
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* @param dev Device struct
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* @return 0 if successful, failed otherwise.
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*/
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static int reg_595_init(const struct device *dev) {
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const struct reg_595_config *const config = dev->config;
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struct reg_595_drv_data *const drv_data = (struct reg_595_drv_data *const)dev->data;
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if (!device_is_ready(config->bus.bus)) {
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LOG_ERR("Unable to get SPI bus device");
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return -ENODEV;
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}
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k_sem_init(&drv_data->lock, 1, 1);
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return 0;
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}
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#define GPIO_PORT_PIN_MASK_FROM_NGPIOS(ngpios) ((gpio_port_pins_t)(((uint64_t)1 << (ngpios)) - 1U))
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#define GPIO_PORT_PIN_MASK_FROM_DT_INST(inst) \
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GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(inst, ngpios))
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#define REG_595_INIT(n) \
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static struct reg_595_config reg_595_##n##_config = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.bus = \
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SPI_DT_SPEC_INST_GET(n, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0), \
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.ngpios = DT_INST_PROP(n, ngpios), \
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}; \
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\
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static struct reg_595_drv_data reg_595_##n##_drvdata = {}; \
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\
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/* This has to init after SPI master */ \
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DEVICE_DT_INST_DEFINE(n, reg_595_init, NULL, ®_595_##n##_drvdata, ®_595_##n##_config, \
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POST_KERNEL, CONFIG_GPIO_595_INIT_PRIORITY, &api_table);
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DT_INST_FOREACH_STATUS_OKAY(REG_595_INIT)
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@ -0,0 +1,33 @@
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#
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# Copyright (c) 2022 The ZMK Contributors
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#
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# SPDX-License-Identifier: MIT
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#
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description: >
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This is a representation of the 595 Shift Register.
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compatible: "zmk,gpio-595"
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include: [gpio-controller.yaml, spi-device.yaml]
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properties:
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label:
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required: true
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"#gpio-cells":
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const: 2
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ngpios:
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type: int
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required: true
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enum:
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- 8
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- 16
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- 24
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- 32
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description: Number of gpios supported
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gpio-cells:
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- pin
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- flags
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