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Merge pull request #166 from Nicell/boards/dz60rgb 

Add DZ60RGB Rev1 Definition
This commit is contained in:
Pete Johanson 2020-09-09 23:10:22 -04:00 committed by GitHub
parent 050a6fac46 ceda57ddfd
commit 5005aa4cd4
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10 changed files with 262 additions and 3 deletions
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7
app/boards/arm/dz60rgb/CMakeLists.txt Normal file
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# SPDX-License-Identifier: MIT
if(CONFIG_PINMUX)
zephyr_library()
zephyr_library_sources(pinmux.c)
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
endif()

6
app/boards/arm/dz60rgb/Kconfig.board Normal file
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# Copyright (c) 2020 Nick Winans
# SPDX-License-Identifier: MIT
config BOARD_DZ60RGB_REV1
bool "DZ60RGB Keyboard"
depends on SOC_STM32F303XC

14
app/boards/arm/dz60rgb/Kconfig.defconfig Normal file
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# DZ60RGB keyboard configuration
# Copyright (c) 2020 Nick Winans
# SPDX-License-Identifier: MIT
if BOARD_DZ60RGB_REV1
config ZMK_KEYBOARD_NAME
default "DZ60RGB Rev 1"
config ZMK_USB
default y
endif # BOARD_DZ60RGB_REV1

7
app/boards/arm/dz60rgb/board.cmake Normal file
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# SPDX-License-Identifier: MIT
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
board_runner_args(jlink "--device=STM32F303CC" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

88
app/boards/arm/dz60rgb/dz60rgb_rev1.dts Normal file
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/*
* Copyright (c) 2020 Nick Winans
*
* SPDX-License-Identifier: MIT
*/
/dts-v1/;
#include <st/f3/stm32f303Xc.dtsi>
#include <dt-bindings/zmk/matrix-transform.h>
/ {
model = "DZ60RGB, Rev 1";
compatible = "dz60rgb,rev1", "st,stm32f303";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zmk,kscan = &kscan0;
zmk,matrix_transform = &default_transform;
};
default_transform: keymap_transform_0 {
compatible = "zmk,matrix-transform";
columns = <14>;
rows = <5>;
map = <
RC(0,0) RC(0,1) RC(0,2) RC(0,3) RC(0,4) RC(0,5) RC(0,6) RC(0,7) RC(0,8) RC(0,9) RC(0,10) RC(0,11) RC(0,12) RC(0,13)
RC(1,0) RC(1,1) RC(1,2) RC(1,3) RC(1,4) RC(1,5) RC(1,6) RC(1,7) RC(1,8) RC(1,9) RC(1,10) RC(1,11) RC(1,12) RC(1,13)
RC(2,0) RC(2,1) RC(2,2) RC(2,3) RC(2,4) RC(2,5) RC(2,6) RC(2,7) RC(2,8) RC(2,9) RC(2,10) RC(2,11) RC(2,13)
RC(3,0) RC(3,1) RC(3,2) RC(3,3) RC(3,4) RC(3,5) RC(3,6) RC(3,7) RC(3,8) RC(3,9) RC(3,10) RC(3,11) RC(3,13)
RC(4,0) RC(4,1) RC(4,2) RC(4,5) RC(4,8) RC(4,9) RC(4,10) RC(4,11) RC(4,13)
>;
};
kscan0: kscan {
compatible = "zmk,kscan-gpio-matrix";
label = "KSCAN";
diode-direction = "col2row";
row-gpios
= <&gpioa 9 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
, <&gpiob 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
, <&gpiob 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
, <&gpiob 14 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
, <&gpiob 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>
;
col-gpios
= <&gpioa 6 GPIO_ACTIVE_HIGH>
, <&gpioa 7 GPIO_ACTIVE_HIGH>
, <&gpiob 0 GPIO_ACTIVE_HIGH>
, <&gpiob 13 GPIO_ACTIVE_HIGH>
, <&gpiob 15 GPIO_ACTIVE_HIGH>
, <&gpioa 8 GPIO_ACTIVE_HIGH>
, <&gpioa 15 GPIO_ACTIVE_HIGH>
, <&gpiob 3 GPIO_ACTIVE_HIGH>
, <&gpiob 4 GPIO_ACTIVE_HIGH>
, <&gpiob 5 GPIO_ACTIVE_HIGH>
, <&gpiob 8 GPIO_ACTIVE_HIGH>
, <&gpiob 9 GPIO_ACTIVE_HIGH>
, <&gpioc 13 GPIO_ACTIVE_HIGH>
, <&gpioc 14 GPIO_ACTIVE_HIGH>
;
};
};
&usb {
status = "okay";
};
&flash0 {
/*
* For more information, see:
* http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions
*/
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set 6Kb of storage at the end of the 256Kb of flash */
storage_partition: partition@3e800 {
label = "storage";
reg = <0x0003e800 0x00001800>;
};
};
};

25
app/boards/arm/dz60rgb/dz60rgb_rev1.keymap Normal file
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#include <behaviors.dtsi>
#include <dt-bindings/zmk/keys.h>
/ {
keymap {
compatible = "zmk,keymap";
default_layer {
// ------------------------------------------------------------------------------------------
// | ESC | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 0 | - | = | BKSP |
// | TAB | Q | W | E | R | T | Y | U | I | O | P | [ | ] | "|" |
// | CAPS | A | S | D | F | G | H | J | K | L | ; | ' | ENTER |
// | SHIFT | Z | X | C | V | B | N | M | , | . | SHIFT(/) | ^ | DEL |
// | CTL | WIN | ALT | SPACE | ALT | MO(1) | <- | v | -> |
// ------------------------------------------------------------------------------------------
bindings = <
&kp ESC &kp NUM_1 &kp NUM_2 &kp NUM_3 &kp NUM_4 &kp NUM_5 &kp NUM_6 &kp NUM_7 &kp NUM_8 &kp NUM_9 &kp NUM_0 &kp MINUS &kp EQL &kp BKSP
&kp TAB &kp Q &kp W &kp E &kp R &kp T &kp Y &kp U &kp I &kp O &kp P &kp LBKT &kp RBKT &kp BSLH
&kp CLCK &kp A &kp S &kp D &kp F &kp G &kp H &kp J &kp K &kp L &kp SCLN &kp QUOT &kp RET
&kp LSFT &kp Z &kp X &kp C &kp V &kp B &kp N &kp M &kp CMMA &kp DOT &mt MOD_RSFT FSLH &kp UARW &kp DEL
&kp LCTL &kp LGUI &kp LALT &kp SPC &kp RALT &mo 1 &kp LARW &kp DARW &kp RARW
>;
};
};
};

19
app/boards/arm/dz60rgb/dz60rgb_rev1.yaml Normal file
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@ -0,0 +1,19 @@
identifier: DZ60RGB_rev1
name: DZ60RGBREV1
type: keyboard
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 40
supported:
- gpio
- i2c
- counter
- spi
- usb_device
- lsm303dlhc
- nvs
- can
- kscan

27
app/boards/arm/dz60rgb/dz60rgb_rev1_defconfig Normal file
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# SPDX-License-Identifier: MIT
CONFIG_SOC_SERIES_STM32F3X=y
CONFIG_SOC_STM32F303XC=y
# 72MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# enable pinmux
CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
# Clock configuration for Cube Clock control driver
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_PREDIV=1
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1

69
app/boards/arm/dz60rgb/pinmux.c Normal file
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/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SPDX-License-Identifier: MIT
*/
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <drivers/pinmux.h>
#include <sys/sys_io.h>
#include <pinmux/stm32/pinmux_stm32.h>
/* pin assignments for STM32F3DISCOVERY board */
static const struct pin_config pinconf[] = {
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usart1), okay) && CONFIG_SERIAL
{STM32_PIN_PC4, STM32F3_PINMUX_FUNC_PC4_USART1_TX},
{STM32_PIN_PC5, STM32F3_PINMUX_FUNC_PC5_USART1_RX},
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usart2), okay) && CONFIG_SERIAL
{STM32_PIN_PA2, STM32F3_PINMUX_FUNC_PA2_USART2_TX},
{STM32_PIN_PA3, STM32F3_PINMUX_FUNC_PA3_USART2_RX},
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay) && CONFIG_I2C
{STM32_PIN_PB6, STM32F3_PINMUX_FUNC_PB6_I2C1_SCL},
{STM32_PIN_PB7, STM32F3_PINMUX_FUNC_PB7_I2C1_SDA},
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c2), okay) && CONFIG_I2C
{STM32_PIN_PA9, STM32F3_PINMUX_FUNC_PA9_I2C2_SCL},
{STM32_PIN_PA10, STM32F3_PINMUX_FUNC_PA10_I2C2_SDA},
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(spi1), okay) && CONFIG_SPI
#ifdef CONFIG_SPI_STM32_USE_HW_SS
{STM32_PIN_PA4, STM32F3_PINMUX_FUNC_PA4_SPI1_NSS},
#endif /* CONFIG_SPI_STM32_USE_HW_SS */
{STM32_PIN_PA5, STM32F3_PINMUX_FUNC_PA5_SPI1_SCK},
{STM32_PIN_PA6, STM32F3_PINMUX_FUNC_PA6_SPI1_MISO},
{STM32_PIN_PA7, STM32F3_PINMUX_FUNC_PA7_SPI1_MOSI},
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(spi2), okay) && CONFIG_SPI
#ifdef CONFIG_SPI_STM32_USE_HW_SS
{STM32_PIN_PB12, STM32F3_PINMUX_FUNC_PB12_SPI2_NSS},
#endif /* CONFIG_SPI_STM32_USE_HW_SS */
{STM32_PIN_PB13, STM32F3_PINMUX_FUNC_PB13_SPI2_SCK},
{STM32_PIN_PB14, STM32F3_PINMUX_FUNC_PB14_SPI2_MISO},
{STM32_PIN_PB15, STM32F3_PINMUX_FUNC_PB15_SPI2_MOSI},
#endif
#ifdef CONFIG_USB_DC_STM32
{STM32_PIN_PA11, STM32F3_PINMUX_FUNC_PA11_USB_DM},
{STM32_PIN_PA12, STM32F3_PINMUX_FUNC_PA12_USB_DP},
#endif /* CONFIG_USB_DC_STM32 */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(can1), okay) && CONFIG_CAN
{STM32_PIN_PD0, STM32F3_PINMUX_FUNC_PD0_CAN1_RX},
{STM32_PIN_PD1, STM32F3_PINMUX_FUNC_PD1_CAN1_TX},
#endif
};
static int pinmux_stm32_init(struct device *port)
{
ARG_UNUSED(port);
stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
return 0;
}
SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1,
CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);

3
app/boards/arm/planck/planck_rev6_defconfig
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@ -20,9 +20,6 @@ CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# however, the board does not have an external oscillator, so just use
# the 8MHz clock signal coming from integrated STLink
CONFIG_CLOCK_STM32_HSE_BYPASS=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_PREDIV=1
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9