From 88d9220f561578ef80364aa9130eae3c792f9f7a Mon Sep 17 00:00:00 2001
From: Michael Colton <michaelrcolton@gmail.com>
Date: Wed, 11 May 2016 16:57:45 -0600
Subject: [PATCH] This fixes (I think) the ADC issue. Or rather, interprets the
 already correct values correctly. Anyway. I think we are good, though more
 testing would be nice. I compared the F4 display performance to the F7 to see
 if the flickering/shimmering effect was there. It was not..... because the
 display was scrolling so slowly by comparison! The F7 is so fast that it was
 sometimes calculating and drawing the waterfall twice! Should be better now,
 but I may want to slow it down further. Also some changes to the power
 up/clock settings functions. Turns out there were two, not sure which is
 better or more complete. They both work well enough for now.

So with this, I think the F7 is now doing everything the F4 was doing, and can become the official chip of the next board revision.
---
 Hardware/PSDR.sch                 | Bin 525874 -> 521505 bytes
 Source/include/main.h             |   4 +-
 Source/src/_initialize_hardware.c |   2 +-
 Source/src/adc.c                  |  24 ++++---
 Source/src/main.c                 | 102 ++++++++++++++++++++----------
 5 files changed, 90 insertions(+), 42 deletions(-)

diff --git a/Hardware/PSDR.sch b/Hardware/PSDR.sch
index 7fb5bf80ff77385fd9a0a75dd19935b3b8c64e9a..8bdb7e10e0568583c2c777d6d663f0f960eb7168 100644
GIT binary patch
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diff --git a/Source/include/main.h b/Source/include/main.h
index dc397f8..74b222a 100644
--- a/Source/include/main.h
+++ b/Source/include/main.h
@@ -36,8 +36,10 @@
 
 #ifdef PSDR257
 //#define HSE_VALUE 26000000
-#define ARM_MATH_CM7
+//#define ARM_MATH_CM7
 //#include "stm32f756xx.h"
+#define  ART_ACCLERATOR_ENABLE 1
+
 #include "stm32f7xx.h"
 #include "stm32f7xx_hal_conf.h"
 #include "stm32f7xx_hal.h"
diff --git a/Source/src/_initialize_hardware.c b/Source/src/_initialize_hardware.c
index 6b58998..1170c94 100644
--- a/Source/src/_initialize_hardware.c
+++ b/Source/src/_initialize_hardware.c
@@ -152,7 +152,7 @@ SystemClock_Config (void)
   RCC_OscInitStruct.PLL.PLLM = (HSI_VALUE / 1000000u);
 #endif
 
-  RCC_OscInitStruct.PLL.PLLN = 216; /* 192 MHz */
+  RCC_OscInitStruct.PLL.PLLN = 432; /* 192 MHz */
   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
   RCC_OscInitStruct.PLL.PLLQ = 8; /* To make USB work. */
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
diff --git a/Source/src/adc.c b/Source/src/adc.c
index d0f96c8..35a7aad 100644
--- a/Source/src/adc.c
+++ b/Source/src/adc.c
@@ -18,8 +18,10 @@ void initAdc()
 		__GPIOB_CLK_ENABLE();
 		__GPIOC_CLK_ENABLE();
 
-		__ADC_FORCE_RESET();
-		__ADC_RELEASE_RESET();
+		//__ADC_FORCE_RESET();
+		//__ADC_RELEASE_RESET();
+		__HAL_RCC_ADC_FORCE_RESET();
+		__HAL_RCC_ADC_RELEASE_RESET();
 
 		  AdcHandle1.Instance          = ADC1;
 
@@ -87,17 +89,17 @@ void initAdc()
 
 		  sConfig1.Channel = ADC_MIC_CHANNEL;
 		  sConfig1.Rank = 1;
-		  sConfig1.SamplingTime = ADC_SAMPLETIME_3CYCLES;
+		  sConfig1.SamplingTime = ADC_SAMPLETIME_15CYCLES;
 		  sConfig1.Offset = 0;
 
 		  sConfig2.Channel = ADC_RX_I_CHANNEL;
 		  sConfig2.Rank = 1;
-		  sConfig2.SamplingTime = ADC_SAMPLETIME_3CYCLES;
+		  sConfig2.SamplingTime = ADC_SAMPLETIME_15CYCLES;
 		  sConfig2.Offset = 0;
 
 		  sConfig3.Channel = ADC_RX_Q_CHANNEL;
 		  sConfig3.Rank = 1;
-		  sConfig3.SamplingTime = ADC_SAMPLETIME_3CYCLES;
+		  sConfig3.SamplingTime = ADC_SAMPLETIME_15CYCLES;
 		  sConfig3.Offset = 0;
 
 		  if(HAL_ADC_ConfigChannel(&AdcHandle1, &sConfig1) != HAL_OK)
@@ -133,9 +135,15 @@ void initAdc()
 		      //while(HAL_ADC_GetState(&AdcHandle1) != HAL_ADC_STATE_REG_EOC);
 
 		     		    /* Check if the continous conversion of regular channel is finished */
-		    if(HAL_ADC_GetState(&AdcHandle1) == 0x300 /*HAL_ADC_STATE_REG_EOC*/
-		    		&& HAL_ADC_GetState(&AdcHandle2) == 0x300 /*HAL_ADC_STATE_REG_EOC*/
-		    		&& HAL_ADC_GetState(&AdcHandle3) == 0x300 /*HAL_ADC_STATE_REG_EOC*/)
+//		    if(HAL_ADC_GetState(&AdcHandle1) == 0x300 /*HAL_ADC_STATE_REG_EOC*/
+//		    		&& HAL_ADC_GetState(&AdcHandle2) == 0x300 /*HAL_ADC_STATE_REG_EOC*/
+//		    		&& HAL_ADC_GetState(&AdcHandle3) == 0x300 /*HAL_ADC_STATE_REG_EOC*/)
+
+		      if(HAL_IS_BIT_SET(HAL_ADC_GetState(&AdcHandle1), HAL_ADC_STATE_REG_EOC) &&
+		          HAL_IS_BIT_SET(HAL_ADC_GetState(&AdcHandle2), HAL_ADC_STATE_REG_EOC) &&
+		          HAL_IS_BIT_SET(HAL_ADC_GetState(&AdcHandle3), HAL_ADC_STATE_REG_EOC))
+
+
 		    {
 		      /*##-5- Get the converted value of regular channel  ########################*/
 		      uhADCxConvertedValue1 = HAL_ADC_GetValue(&AdcHandle1);
diff --git a/Source/src/main.c b/Source/src/main.c
index cc05e31..6da0dd3 100644
--- a/Source/src/main.c
+++ b/Source/src/main.c
@@ -44,6 +44,7 @@
 //#pragma GCC diagnostic ignored "-Wreturn-type"
 #pragma GCC diagnostic ignored "-Wfloat-conversion"
 
+static void CPU_CACHE_Enable(void);
 void dac1SetValue(uint16_t value);
 void dac2SetValue(uint16_t value);
 //void ddsPrefix(void);
@@ -96,37 +97,55 @@ unsigned int tone = 0;
 
 uint8_t displayUpdating = 0;
 
-/** System Clock Configuration
-*/
-void SystemClock_Config(void)
-{
-
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  __PWR_CLK_ENABLE();
-
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = 13;
-  RCC_OscInitStruct.PLL.PLLN = 216;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 9;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
-                              |RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
-
-}
+///** System Clock Configuration
+//*/
+//void SystemClock_Config(void)
+//{
+//
+//  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+//  RCC_OscInitTypeDef RCC_OscInitStruct;
+//
+//  __PWR_CLK_ENABLE();
+//
+//  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); //needed?
+//
+//  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+//  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+//  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+//  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+//  RCC_OscInitStruct.PLL.PLLM = 26;
+//  RCC_OscInitStruct.PLL.PLLN = 432;
+//  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+//  RCC_OscInitStruct.PLL.PLLQ = 9;
+//  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+//
+//  HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+//  if(ret != HAL_OK)
+//    {
+//      while(1) { ; }
+//    }
+//
+//  /* Activate the OverDrive to reach the 216 MHz Frequency */
+//    ret = HAL_PWREx_EnableOverDrive();
+//    if(ret != HAL_OK)
+//    {
+//      while(1) { ; }
+//    }
+//
+//  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_HCLK |RCC_CLOCKTYPE_PCLK1
+//                              |RCC_CLOCKTYPE_PCLK2;
+//  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+//  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+//  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+//  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+//
+//  ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
+//  if(ret != HAL_OK)
+//    {
+//      while(1) { ; }
+//    }
+//
+//}
 
 void polarToRect(float m, float a, float32_t* x, float32_t* y)
 {
@@ -777,9 +796,14 @@ int
 main(int argc, char* argv[])
 {
 
+  /* Enable the CPU Cache */
+  CPU_CACHE_Enable();
+
+
+
 	HAL_Init();
 
-	SystemClock_Config();
+	//SystemClock_Config();
 
 	//HAL_RCC_OscConfig()
 	//	RCC_ClkInitStruct clockInitStructure;
@@ -1974,6 +1998,20 @@ void dac2SetValue(uint16_t value)
 	HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value);
 }
 
+/**
+  * @brief  CPU L1-Cache enable.
+  * @param  None
+  * @retval None
+  */
+static void CPU_CACHE_Enable(void)
+{
+  /* Enable I-Cache */
+  SCB_EnableICache();
+
+  /* Enable D-Cache */
+  SCB_EnableDCache();
+}
+
 #pragma GCC diagnostic pop
 
 // ----------------------------------------------------------------------------