432 lines
14 KiB
C
432 lines
14 KiB
C
/*
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** cpu.h Motorola M68k, CPU32 and ColdFire cpu-description header-file
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** (c) in 2002,2006-2017 by Frank Wille
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*/
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#define BIGENDIAN 1
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#define LITTLEENDIAN 0
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#define VASM_CPU_M68K 1
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#define MNEMOHTABSIZE 0x4000
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/* maximum number of operands for one mnemonic */
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#define MAX_OPERANDS 6
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/* maximum number of mnemonic-qualifiers per mnemonic */
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#define MAX_QUALIFIERS 1
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/* maximum number of additional command-line-flags for this cpu */
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/* data type to represent a target-address */
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typedef int32_t taddr;
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typedef uint32_t utaddr;
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/* instruction extension */
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#define HAVE_INSTRUCTION_EXTENSION 1
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typedef struct {
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union {
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struct {
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unsigned char flags;
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signed char last_size;
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signed char orig_ext;
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char unused;
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} real;
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struct {
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struct instruction *next;
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} copy;
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} un;
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} instruction_ext;
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#define IFL_RETAINLASTSIZE 1 /* retain current last_size value */
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#define IFL_UNSIZED 2 /* instruction had no size extension */
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/* we use OPTS atoms for cpu-specific options */
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#define HAVE_CPU_OPTS 1
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typedef struct {
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int cmd;
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int arg;
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} optcmd;
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/* optcmd commands - warning: print_cpu_opts() depends on the order! */
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enum {
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OCMD_NOP,
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OCMD_CPU,
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OCMD_FPU,
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OCMD_SDREG,
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OCMD_NOOPT,
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OCMD_OPTGEN,
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OCMD_OPTMOVEM,
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OCMD_OPTPEA,
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OCMD_OPTCLR,
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OCMD_OPTST,
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OCMD_OPTLSL,
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OCMD_OPTMUL,
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OCMD_OPTDIV,
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OCMD_OPTFCONST,
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OCMD_OPTBRAJMP,
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OCMD_OPTJBRA,
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OCMD_OPTPC,
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OCMD_OPTBRA,
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OCMD_OPTDISP,
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OCMD_OPTABS,
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OCMD_OPTMOVEQ,
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OCMD_OPTQUICK,
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OCMD_OPTBRANOP,
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OCMD_OPTBDISP,
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OCMD_OPTODISP,
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OCMD_OPTLEA,
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OCMD_OPTLQUICK,
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OCMD_OPTIMMADDR,
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OCMD_OPTSPEED,
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OCMD_SMALLCODE,
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OCMD_SMALLDATA,
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OCMD_OPTWARN,
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OCMD_CHKPIC,
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OCMD_CHKTYPE,
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OCMD_NOWARN
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};
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/* minimum instruction alignment */
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#define INST_ALIGN 2
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/* default alignment for n-bit data */
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#define DATA_ALIGN(n) ((n<=8)?1:2)
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/* operand class for n-bit data definitions */
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#define DATA_OPERAND(n) m68k_data_operand(n)
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/* returns true when instruction is valid for selected cpu */
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#define MNEMONIC_VALID(n) m68k_available(n)
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/* parse cpu-specific directives with label */
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#define PARSE_CPU_LABEL(l,s) parse_cpu_label(l,s)
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/* type to store each operand */
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typedef struct {
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signed char mode;
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signed char reg;
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uint16_t format; /* used for (d8,An/PC,Rn) and ext.addr.modes */
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unsigned char bf_offset; /* bitfield offset, k-factor or MAC Upper Word */
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unsigned char bf_width; /* bitfield width or MAC-MASK '&' */
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int8_t basetype[2]; /* BASE_OK=normal, BASE=PCREL=pc-relative base */
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uint32_t flags;
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expr *value[2]; /* immediate, abs. or displacem. expression */
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/* filled during instruction_size(): */
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taddr extval[2]; /* evaluated expression from value[0/1] */
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symbol *base[2]; /* symbol base for value[0/1], NULL otherwise */
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} operand;
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/* flags */
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/* Note: FL_CheckMask bits are used together with optype.flags OTF-bits */
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#define FL_ExtVal0 1 /* extval[0] is set */
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#define FL_ExtVal1 2 /* extval[1] is set */
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#define FL_UsesFormat 4 /* operand uses format word */
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#define FL_020up 8 /* 020+ addressing mode */
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#define FL_noCPU32 0x10 /* addressing mode not available for CPU32 */
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#define FL_BFoffsetDyn 0x20 /* dynamic bitfield offset specified */
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#define FL_BFwidthDyn 0x40 /* dynamic bitfield width specified */
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#define FL_DoNotEval 0x80 /* do not evaluate, extval and base are ok */
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/*#define FL_PossRegList 0x80 parser is not sure if operand is RegList */
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#define FL_NoOptBase 0x100 /* never optimize base displacement */
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#define FL_NoOptOuter 0x200 /* never optimize outer displacement */
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#define FL_NoOpt 0x300 /* never optimize this whole operand */
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#define FL_ZBase 0x400 /* ZAn base register specified */
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#define FL_ZIndex 0x800 /* ZRn index register specified */
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#define FL_BaseReg 0x1000 /* BASEREG expression in exp.value[0] */
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#define FL_BnReg 0x4000 /* Apollo: Bn register instead of An */
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#define FL_MAC 0x8000 /* ColdFire MAC specific extensions */
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#define FL_Bitfield 0x10000 /* operand uses bf_offset/bf_width */
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#define FL_DoubleReg 0x20000 /* Dm:Dn or (Rm):(Rn), where both registers
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are put into "reg": 0nnn0mmm */
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#define FL_KFactor 0x40000 /* k-factor <ea>{#n} or <ea>{Dn}, which
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can be found in bf_offset */
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#define FL_FPSpec 0x80000 /* special FPU reg. FPIAR/FPCR/FPSR only */
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#define FL_CheckMask 0xfc000 /* bits to check, when comparing with
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flags from struct optype */
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/* addressing modes */
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#define MODE_Dn 0
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#define MODE_An 1
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#define MODE_AnIndir 2
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#define MODE_AnPostInc 3
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#define MODE_AnPreDec 4
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#define MODE_An16Disp 5
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#define MODE_An8Format 6 /* uses format word */
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#define MODE_Extended 7 /* reg determines addressing mode */
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#define MODE_FPn 8 /* FPU register */
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#define MODE_SpecReg 9 /* reg determines index into SpecRegs */
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/* reg encodings for MODE_Extended: */
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#define REG_AbsShort 0
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#define REG_AbsLong 1
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#define REG_PC16Disp 2
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#define REG_PC8Format 3 /* uses format word */
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#define REG_Immediate 4
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#define REG_RnList 5 /* An/Dn register list in value[0] */
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#define REG_FPnList 6 /* FPn register list in value[0] */
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/* format word */
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#define FW_IndexAn 0x8000
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#define FW_IndexReg_Shift 12
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#define FW_IndexReg(n) ((n)<<FW_IndexReg_Shift)
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#define FW_LongIndex 0x0800
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#define FW_Scale_Shift 9
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#define FW_Scale(n) ((n)<<FW_Scale_Shift)
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#define FW_FullFormat 0x0100
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#define FW_BaseSuppress 0x0080
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#define FW_IndexSuppress 0x0040
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#define FW_BDSize_Shift 4
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#define FW_BDSize(n) ((n)<<FW_BDSize_Shift)
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#define FW_getBDSize(n) (((n)>>FW_BDSize_Shift)&3)
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#define FW_Postindexed 0x0004
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#define FW_IndSize(n) (n)
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#define FW_getIndSize(n) (n&3)
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#define FW_None 0
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#define FW_Null 1
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#define FW_Word 2
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#define FW_Long 3
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#define FW_SizeMask 3
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/* register macros */
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#define REGAn 8
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#define REGPC 0x10
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#define REGBn 0x20 /* Apollo only */
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#define REGZero 0x80
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#define REGisAn(n) ((n)®An)
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#define REGisDn(n) (!((n)®An))
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#define REGisPC(n) ((n)®PC)
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#define REGisZero(n) ((n)®Zero)
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#define REGisBn(n) ((n)®Bn) /* Apollo only */
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#define REGget(n) ((n)&(REGAn-1))
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#define REGgetA(n) ((n)&(REGPC-1))
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#define REGext_Shift 8
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#define REGext(n) (((n)&0x700)>>REGext_Shift)
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#define REGscale_Shift 12
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#define REGscale(n) (((n)&0x3000)>>REGscale_Shift)
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/* MAC scale-factor, stored as value[0] */
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#define MACSF_None 0
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#define MACSF_ShiftLeft 1
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#define MACSF_ShiftRight 3
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/* special CPU registers */
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struct specreg {
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char *name;
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int code; /* -1 means no code, syntax-check only */
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uint32_t available;
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};
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/* extension codes */
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#define EXT_BYTE 1
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#define EXT_WORD 2
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#define EXT_LONG 3
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#define EXT_SINGLE 4
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#define EXT_DOUBLE 5
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#define EXT_EXTENDED 6
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#define EXT_PACKED 7
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#define EXT_UPPER 2 /* ColdFire MAC upper register word */
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#define EXT_LOWER 3 /* ColdFire MAC lower register word */
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#define EXT_MASK 7
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struct addrmode {
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signed char mode;
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signed char reg;
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};
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#define AM_Dn 0
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#define AM_An 1
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#define AM_AnIndir 2
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#define AM_AnPostInc 3
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#define AM_AnPreDec 4
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#define AM_An16Disp 5
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#define AM_An8Format 6
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#define AM_AbsShort 7
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#define AM_AbsLong 8
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#define AM_PC16Disp 9
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#define AM_PC8Format 10
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#define AM_Immediate 11
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#define AM_RnList 12
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#define AM_FPnList 13
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#define AM_FPn 14
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#define AM_SpecReg 15
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/* operand types */
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struct optype {
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uint16_t modes; /* addressing modes allowed (0-15, see above) */
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uint32_t flags;
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unsigned char first;
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unsigned char last;
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};
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/* flags */
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/* Note: Do not allocate bits from FL_CheckMask! */
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#define OTF_NOSIZE 1 /* this addr. mode requires no additional bytes */
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#define OTF_BRANCH 2 /* branch instruction */
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#define OTF_DATA 4 /* data definition */
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#define OTF_FLTIMM 8 /* base10 immediate values are floating point */
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#define OTF_QUADIMM 0x10 /* immediate values are 64 bits */
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#define OTF_SPECREG 0x20 /* check for special registers during parse */
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#define OTF_SRRANGE 0x40 /* check range between first/last only */
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#define OTF_REGLIST 0x80 /* register list required, even when single reg. */
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#define OTF_CHKVAL 0x100 /* compare op. value against first/last */
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#define OTF_CHKREG 0x200 /* compare op. register against first/last */
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#define OTF_VXRNG2 0x400 /* Apollo AMMX Rn:Rn+1 vector register range */
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#define OTF_VXRNG4 0x800 /* Apollo AMMX Rn-Rn+3 vector register range */
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/* additional mnemonic data */
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typedef struct {
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uint16_t place[MAX_OPERANDS];
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uint16_t opcode[2];
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uint16_t size;
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uint32_t available;
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} mnemonic_extension;
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/* size qualifiers, lowest two bits specify opcode size in words! */
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#define SIZE_UNSIZED 0
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#define SIZE_BYTE 0x100
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#define SIZE_WORD 0x200
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#define SIZE_LONG 0x400
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#define SIZE_SINGLE 0x800
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#define SIZE_DOUBLE 0x1000
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#define SIZE_EXTENDED 0x2000
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#define SIZE_PACKED 0x4000
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#define SIZE_MASK 0x7f00
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#define SIZE_UNAMBIG 0x8000 /* only a single size allowed for this mnemonic */
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#define S_CFCHECK 0x80 /* SIZE_LONG only, when mcf (Coldfire) set */
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#define S_NONE 4
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#define S_STD S_NONE+4 /* 1st word, bits 6-7 */
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#define S_STD1 S_STD+4 /* 1st word, bits 6-7, b=1,w=2,l=3 */
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#define S_HI S_STD1+4 /* 1st word, bits 9-10 */
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#define S_CAS S_HI+4 /* 1st word, bits 9-10, b=1,w=2,l=3 */
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#define S_MOVE S_CAS+4 /* move instruction, 1st word bits 12-13 */
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#define S_WL8 S_MOVE+4 /* w/l flag in 1st word bit 8 */
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#define S_LW7 S_WL8+4 /* l/w flag in 1st word bit 7 */
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#define S_WL6 S_LW7+4 /* w/l flag in 1st word bit 6 */
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#define S_TRAP S_WL6+4 /* 1st word, bits 1-0, w=2, l=3 */
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#define S_EXT S_TRAP+4 /* 2nd word, bits 6-7 */
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#define S_FP S_EXT+4 /* 2nd word, bits 12-10 (l=0,s,x,p,w,d,b) */
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#define S_MAC S_FP+4 /* w/l flag in 2nd word bit 11 */
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#define S_OPCODE_SIZE(n) (n&3)
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#define S_SIZEMODE(n) (n&0x7c)
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/* short cuts */
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#define UNS SIZE_UNSIZED
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#define B SIZE_BYTE
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#define W SIZE_WORD
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#define L SIZE_LONG
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#define Q SIZE_DOUBLE
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#define SBW (SIZE_BYTE|SIZE_WORD|SIZE_SINGLE) /* .s = .b for branches */
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#define SBWL (SIZE_BYTE|SIZE_WORD|SIZE_LONG|SIZE_SINGLE)
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#define BW (SIZE_BYTE|SIZE_WORD)
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#define WL (SIZE_WORD|SIZE_LONG)
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#define BWL (SIZE_BYTE|SIZE_WORD|SIZE_LONG)
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#define CFWL (SIZE_WORD|SIZE_LONG|S_CFCHECK)
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#define CFBWL (SIZE_BYTE|SIZE_WORD|SIZE_LONG|S_CFCHECK)
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#define ANY (SIZE_BYTE|SIZE_WORD|SIZE_LONG|SIZE_SINGLE|SIZE_DOUBLE| \
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SIZE_EXTENDED|SIZE_PACKED)
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#define CFANY (SIZE_BYTE|SIZE_WORD|SIZE_LONG|SIZE_SINGLE|SIZE_DOUBLE)
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#define FX SIZE_EXTENDED
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#define FD SIZE_DOUBLE
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/* operand insertion info */
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struct oper_insert {
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unsigned char mode; /* insert mode (see below) */
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unsigned char size; /* number of bits to insert */
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unsigned char pos; /* bit position for inserted value in stream */
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unsigned char flags;
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void (*insert)(unsigned char *,struct oper_insert *,operand *);
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};
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/* insert modes */
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#define M_nop 0 /* do nothing for this operand */
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#define M_noea 1 /* don't store ea, only extension words */
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#define M_ea 2 /* insert mode/reg in lowest 6 bits */
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#define M_high_ea 3 /* insert reg/mode in bits 11-6 (MOVE) */
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#define M_bfea 4 /* insert std. ea and bitfield offset/width */
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#define M_kfea 5 /* insert std. ea and k-factor/dest.format */
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#define M_func 6 /* use insert() function */
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#define M_branch 7 /* extval0 contains branch label */
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#define M_val0 8 /* extval0 at specified position */
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#define M_reg 9 /* insert reg at specified position */
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/* flags */
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#define IIF_MASK 1 /* value 2^size is represented by a 0 (M_val0)
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recognize MASK-flag for MAC instr. (M_ea) */
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#define IIF_BCC 2 /* Bcc branch, opcode is modified */
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#define IIF_REVERSE 4 /* store bits in reverse order (M_val0) */
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#define IIF_NOMODE 8 /* don't store ea mode specifier in opcode */
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#define IIF_SIGNED 16 /* value is signed (M_val0) */
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#define IIF_3Q 64 /* MOV3Q: -1 is written as 0 (M_val0) */
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#define IIF_ABSVAL 128 /* make sure first expr. is absolute (M_func) */
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/* redefinition for AMMX special registers (M_func) */
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#define IIF_A 8 /* RegBit 4 to A-bit (bit-position 8) */
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#define IIF_B 7 /* RegBit 4 to B-bit (bit-position 7) */
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#define IIF_D 6 /* RegBit 4 to D-bit (bit-position 6) */
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/* CPU models and their type-flags */
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struct cpu_models {
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char name[8];
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uint32_t type;
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};
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/* cpu types for availability check - warning: order is important */
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#define CPUMASK 0x00ffffff
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#define m68000 0x00000001
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#define m68010 0x00000002
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#define m68020 0x00000004
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#define m68030 0x00000008
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#define m68040 0x00000010
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#define m68060 0x00000020
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#define m68881 0x00000040
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#define m68882 m68881
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#define m68851 0x00000080
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#define cpu32 0x00000100
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#define mcfa 0x00000200
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#define mcfaplus 0x00000400
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#define mcfb 0x00000800
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#define mcfc 0x00001000
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#define mcfhwdiv 0x00002000
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#define mcfmac 0x00004000
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#define mcfemac 0x00008000
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#define mcfusp 0x00010000
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#define mcffpu 0x00020000
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#define mcfmmu 0x00040000
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#define ac68080 0x00100000
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#define mgas 0x20000000 /* a GNU-as specific mnemonic */
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#define malias 0x40000000 /* a bad alias which we should warn about */
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#define mfpu 0x80000000 /* just to check if CP-ID needs to be inserted */
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/* handy aliases */
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#define m68k (m68000|m68010|m68020|m68030|m68040|m68060)
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#define apollo (ac68080)
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#define mcf (mcfa|mcfaplus|mcfb|mcfc)
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#define mcf_all (mcfa|mcfaplus|mcfb|mcfc|mcfhwdiv|mcfmac|mcfemac|mcfusp|mcffpu|mcfmmu)
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#define mfloat (mfpu|m68881|m68882|m68040|m68060)
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#define mmmu (m68851|m68030|m68040|m68060)
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#define m68040up (m68040|m68060|apollo)
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#define m68030up (m68030|m68040up)
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#define m68020up (m68020|m68030up)
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#define m68010up (m68010|cpu32|m68020up)
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#define m68000up (m68000|m68010up)
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/* register symbols */
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#define HAVE_REGSYMS
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#define REGSYMHTSIZE 256
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#define RSTYPE_Dn 0
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#define RSTYPE_An 1
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#define RSTYPE_FPn 2
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#define RSTYPE_Bn 3 /* Apollo only */
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/* MID for a.out format */
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extern int m68k_mid;
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#define MID m68k_mid
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/* exported functions */
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int m68k_available(int);
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int m68k_data_operand(int);
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int parse_cpu_label(char *,char **);
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