150 lines
7.5 KiB
C
150 lines
7.5 KiB
C
/* name, operand 1, operand 2, operand 3, OpCode, Rn pos, CPU model */
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"and", {OP_GPR, OP_GPR, OP_GPR }, {0x80, 2, CPU_ALL},
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"and", {OP_GPR, OP_GPR, OP_IMM }, {0x80, 2, CPU_ALL},
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"or", {OP_GPR, OP_GPR, OP_GPR }, {0x81, 2, CPU_ALL},
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"or", {OP_GPR, OP_GPR, OP_IMM }, {0x81, 2, CPU_ALL},
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"xor", {OP_GPR, OP_GPR, OP_GPR }, {0x82, 2, CPU_ALL},
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"xor", {OP_GPR, OP_GPR, OP_IMM }, {0x82, 2, CPU_ALL},
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"bitc", {OP_GPR, OP_GPR, OP_GPR }, {0x83, 2, CPU_ALL},
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"bitc", {OP_GPR, OP_GPR, OP_IMM }, {0x83, 2, CPU_ALL},
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"add", {OP_GPR, OP_GPR, OP_GPR }, {0x84, 2, CPU_ALL},
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"add", {OP_GPR, OP_GPR, OP_IMM }, {0x84, 2, CPU_ALL},
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"addc", {OP_GPR, OP_GPR, OP_GPR }, {0x85, 2, CPU_ALL},
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"addc", {OP_GPR, OP_GPR, OP_IMM }, {0x85, 2, CPU_ALL},
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"sub", {OP_GPR, OP_GPR, OP_GPR }, {0x86, 2, CPU_ALL},
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"sub", {OP_GPR, OP_GPR, OP_IMM }, {0x86, 2, CPU_ALL},
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"subb", {OP_GPR, OP_GPR, OP_GPR }, {0x87, 2, CPU_ALL},
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"subb", {OP_GPR, OP_GPR, OP_IMM }, {0x87, 2, CPU_ALL},
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"rsb", {OP_GPR, OP_GPR, OP_GPR }, {0x88, 2, CPU_ALL},
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"rsb", {OP_GPR, OP_GPR, OP_IMM }, {0x88, 2, CPU_ALL},
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"rsbb", {OP_GPR, OP_GPR, OP_GPR }, {0x89, 2, CPU_ALL},
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"rsbb", {OP_GPR, OP_GPR, OP_IMM }, {0x89, 2, CPU_ALL},
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"lls", {OP_GPR, OP_GPR, OP_GPR }, {0x8A, 2, CPU_ALL},
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"lls", {OP_GPR, OP_GPR, OP_IMM }, {0x8A, 2, CPU_ALL},
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"lrs", {OP_GPR, OP_GPR, OP_GPR }, {0x8B, 2, CPU_ALL},
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"lrs", {OP_GPR, OP_GPR, OP_IMM }, {0x8B, 2, CPU_ALL},
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"ars", {OP_GPR, OP_GPR, OP_GPR }, {0x8C, 2, CPU_ALL},
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"ars", {OP_GPR, OP_GPR, OP_IMM }, {0x8C, 2, CPU_ALL},
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"rotl", {OP_GPR, OP_GPR, OP_GPR }, {0x8D, 2, CPU_ALL},
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"rotl", {OP_GPR, OP_GPR, OP_IMM }, {0x8D, 2, CPU_ALL},
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"rotr", {OP_GPR, OP_GPR, OP_GPR }, {0x8E, 2, CPU_ALL},
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"rotr", {OP_GPR, OP_GPR, OP_IMM }, {0x8E, 2, CPU_ALL},
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"mul", {OP_GPR, OP_GPR, OP_GPR }, {0x8F, 2, CPU_ALL},
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"mul", {OP_GPR, OP_GPR, OP_IMM }, {0x8F, 2, CPU_ALL},
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"smul", {OP_GPR, OP_GPR, OP_GPR }, {0x90, 2, CPU_ALL},
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"smul", {OP_GPR, OP_GPR, OP_IMM }, {0x90, 2, CPU_ALL},
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"div", {OP_GPR, OP_GPR, OP_GPR }, {0x91, 2, CPU_ALL},
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"div", {OP_GPR, OP_GPR, OP_IMM }, {0x91, 2, CPU_ALL},
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"sdiv", {OP_GPR, OP_GPR, OP_GPR }, {0x92, 2, CPU_ALL},
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"sdiv", {OP_GPR, OP_GPR, OP_IMM }, {0x92, 2, CPU_ALL},
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/* P2 */
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"mov", {OP_GPR, OP_GPR }, {0x40, 1, CPU_ALL},
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"mov", {OP_GPR, OP_IMM }, {0x40, 1, CPU_ALL},
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"swp", {OP_GPR, OP_GPR }, {0x41, 1, CPU_ALL},
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"not", {OP_GPR, OP_GPR }, {0x42, 1, CPU_ALL},
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"not", {OP_GPR, OP_IMM }, {0x42, 1, CPU_ALL},
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"sigxb", {OP_GPR, OP_GPR }, {0x43, 1, CPU_ALL},
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"sigxb", {OP_GPR, OP_IMM }, {0x43, 1, CPU_ALL},
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"sigxw", {OP_GPR, OP_GPR }, {0x44, 1, CPU_ALL},
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"sigxw", {OP_GPR, OP_IMM }, {0x44, 1, CPU_ALL},
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"jmp", {OP_GPR, OP_GPR }, {0x4B, 1, CPU_ALL},
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"jmp", {OP_GPR, OP_IMM }, {0x4B, 1, CPU_ALL},
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"call", {OP_GPR, OP_GPR }, {0x4C, 1, CPU_ALL},
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"call", {OP_GPR, OP_IMM }, {0x4C, 1, CPU_ALL},
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/* Branch */
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"ifeq", {OP_GPR, OP_GPR }, {0x70, 1, CPU_ALL},
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"ifeq", {OP_GPR, OP_IMM }, {0x70, 1, CPU_ALL},
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"ifneq", {OP_GPR, OP_GPR }, {0x71, 1, CPU_ALL},
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"ifneq", {OP_GPR, OP_IMM }, {0x71, 1, CPU_ALL},
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"ifl", {OP_GPR, OP_GPR }, {0x72, 1, CPU_ALL},
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"ifl", {OP_GPR, OP_IMM }, {0x72, 1, CPU_ALL},
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"ifsl", {OP_GPR, OP_GPR }, {0x73, 1, CPU_ALL},
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"ifsl", {OP_GPR, OP_IMM }, {0x73, 1, CPU_ALL},
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"ifle", {OP_GPR, OP_GPR }, {0x74, 1, CPU_ALL},
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"ifle", {OP_GPR, OP_IMM }, {0x74, 1, CPU_ALL},
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"ifsle", {OP_GPR, OP_GPR }, {0x75, 1, CPU_ALL},
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"ifsle", {OP_GPR, OP_IMM }, {0x75, 1, CPU_ALL},
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"ifg", {OP_GPR, OP_GPR }, {0x76, 1, CPU_ALL},
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"ifg", {OP_GPR, OP_IMM }, {0x76, 1, CPU_ALL},
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"ifsg", {OP_GPR, OP_GPR }, {0x77, 1, CPU_ALL},
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"ifsg", {OP_GPR, OP_IMM }, {0x77, 1, CPU_ALL},
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"ifge", {OP_GPR, OP_GPR }, {0x78, 1, CPU_ALL},
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"ifge", {OP_GPR, OP_IMM }, {0x78, 1, CPU_ALL},
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"ifsge", {OP_GPR, OP_GPR }, {0x79, 1, CPU_ALL},
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"ifsge", {OP_GPR, OP_IMM }, {0x79, 1, CPU_ALL},
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"ifbits", {OP_GPR, OP_GPR }, {0x7A, 1, CPU_ALL},
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"ifbits", {OP_GPR, OP_IMM }, {0x7A, 1, CPU_ALL},
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"ifclear", {OP_GPR, OP_GPR }, {0x7B, 1, CPU_ALL},
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"ifclear", {OP_GPR, OP_IMM }, {0x7B, 1, CPU_ALL},
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/* P1 instructions */
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"xchgb", {OP_GPR }, {0x20, 0, CPU_ALL},
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"xchgb", {OP_IMM }, {0x20, 0, CPU_ALL},
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"xchgw", {OP_GPR }, {0x21, 0, CPU_ALL},
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"xchgw", {OP_IMM }, {0x21, 0, CPU_ALL},
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"getpc", {OP_GPR }, {0x22, 0, CPU_ALL},
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"pop", {OP_GPR }, {0x23, 0, CPU_ALL},
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"push", {OP_GPR }, {0x24, 0, CPU_ALL},
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"push", {OP_IMM }, {0x24, 0, CPU_ALL},
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"jmp", {OP_GPR }, {0x25, 0, CPU_ALL},
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"jmp", {OP_IMM }, {0x25, 0, CPU_ALL},
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"call", {OP_GPR }, {0x26, 0, CPU_ALL},
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"call", {OP_IMM }, {0x26, 0, CPU_ALL},
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"rjmp", {OP_GPR }, {0x27, 0, CPU_ALL},
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"rjmp", {OP_IMM }, {0x27, 0, CPU_ALL},
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"rcall", {OP_GPR }, {0x28, 0, CPU_ALL},
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"rcall", {OP_IMM }, {0x28, 0, CPU_ALL},
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"int", {OP_GPR }, {0x29, 0, CPU_ALL},
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"int", {OP_IMM }, {0x29, 0, CPU_ALL},
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/* NP instructions */
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"sleep", { }, {0x00, 0, CPU_ALL},
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"ret", { }, {0x01, 0, CPU_ALL},
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"rfi", { }, {0x02, 0, CPU_ALL},
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/* Load / Store*/
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/* Register Were to read */
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"load", {OP_GPR, OP_GPR, OP_GPR }, {0x93, 2, CPU_ALL},
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"load", {OP_GPR, OP_GPR, OP_IMM }, {0x93, 2, CPU_ALL},
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"load", {OP_GPR, OP_GPR }, {0x45, 1, CPU_ALL},
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"load", {OP_GPR, OP_IMM }, {0x45, 1, CPU_ALL},
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"loadw", {OP_GPR, OP_GPR, OP_GPR }, {0x94, 2, CPU_ALL},
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"loadw", {OP_GPR, OP_GPR, OP_IMM }, {0x94, 2, CPU_ALL},
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"loadw", {OP_GPR, OP_GPR }, {0x46, 1, CPU_ALL},
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"loadw", {OP_GPR, OP_IMM }, {0x46, 1, CPU_ALL},
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"loadb", {OP_GPR, OP_GPR, OP_GPR }, {0x95, 2, CPU_ALL},
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"loadb", {OP_GPR, OP_GPR, OP_IMM }, {0x95, 2, CPU_ALL},
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"loadb", {OP_GPR, OP_GPR }, {0x47, 1, CPU_ALL},
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"loadb", {OP_GPR, OP_IMM }, {0x47, 1, CPU_ALL},
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/* Were to write data to write */
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"store", {OP_GPR, OP_GPR, OP_GPR }, {0x96, 1, CPU_ALL},
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"store", {OP_GPR, OP_IMM, OP_GPR }, {0x96, 1, CPU_ALL},
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"store", {OP_GPR, OP_GPR }, {0x48, 0, CPU_ALL},
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"store", {OP_IMM, OP_GPR }, {0x48, 0, CPU_ALL},
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"storew", {OP_GPR, OP_GPR, OP_GPR }, {0x97, 1, CPU_ALL},
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"storew", {OP_GPR, OP_IMM, OP_GPR }, {0x97, 1, CPU_ALL},
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"storew", {OP_GPR, OP_GPR }, {0x49, 0, CPU_ALL},
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"storew", {OP_IMM, OP_GPR }, {0x49, 0, CPU_ALL},
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"storeb", {OP_GPR, OP_GPR, OP_GPR }, {0x98, 1, CPU_ALL},
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"storeb", {OP_GPR, OP_IMM, OP_GPR }, {0x98, 1, CPU_ALL},
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"storeb", {OP_GPR, OP_GPR }, {0x4A, 0, CPU_ALL},
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"storeb", {OP_IMM, OP_GPR }, {0x4A, 0, CPU_ALL},
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/* TODO Others */
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