181 lines
5.3 KiB
C
181 lines
5.3 KiB
C
{"st", FloatReg|FloatAcc, 0, 0},
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/* 8 bit regs */
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#define AL_INDEX 1
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{"al", Reg8|Acc, 0, 0},
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{"cl", Reg8|ShiftCntReg, 0, 1},
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{"dl", Reg8, 0, 2},
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{"bl", Reg8, 0, 3},
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{"ah", Reg8, 0, 4},
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{"ch", Reg8, 0, 5},
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{"dh", Reg8, 0, 6},
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{"bh", Reg8, 0, 7},
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{"axl", Reg8|Acc, RegRex64, 0},
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{"cxl", Reg8, RegRex64, 1},
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{"dxl", Reg8, RegRex64, 2},
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{"bxl", Reg8, RegRex64, 3},
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{"spl", Reg8, RegRex64, 4},
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{"bpl", Reg8, RegRex64, 5},
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{"sil", Reg8, RegRex64, 6},
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{"dil", Reg8, RegRex64, 7},
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{"r8b", Reg8, RegRex64|RegRex, 0},
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{"r9b", Reg8, RegRex64|RegRex, 1},
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{"r10b", Reg8, RegRex64|RegRex, 2},
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{"r11b", Reg8, RegRex64|RegRex, 3},
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{"r12b", Reg8, RegRex64|RegRex, 4},
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{"r13b", Reg8, RegRex64|RegRex, 5},
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{"r14b", Reg8, RegRex64|RegRex, 6},
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{"r15b", Reg8, RegRex64|RegRex, 7},
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/* 16 bit regs */
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#define AX_INDEX 25
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{"ax", Reg16|Acc, 0, 0},
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{"cx", Reg16, 0, 1},
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{"dx", Reg16|IOPortReg, 0, 2},
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{"bx", Reg16|BaseIndex, 0, 3},
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{"sp", Reg16, 0, 4},
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{"bp", Reg16|BaseIndex, 0, 5},
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{"si", Reg16|BaseIndex, 0, 6},
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{"di", Reg16|BaseIndex, 0, 7},
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{"r8w", Reg16, RegRex, 0},
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{"r9w", Reg16, RegRex, 1},
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{"r10w", Reg16, RegRex, 2},
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{"r11w", Reg16, RegRex, 3},
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{"r12w", Reg16, RegRex, 4},
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{"r13w", Reg16, RegRex, 5},
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{"r14w", Reg16, RegRex, 6},
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{"r15w", Reg16, RegRex, 7},
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/* 32 bit regs */
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#define EAX_INDEX 41
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{"eax", Reg32|BaseIndex|Acc, 0, 0},
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{"ecx", Reg32|BaseIndex, 0, 1},
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{"edx", Reg32|BaseIndex, 0, 2},
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{"ebx", Reg32|BaseIndex, 0, 3},
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{"esp", Reg32, 0, 4},
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{"ebp", Reg32|BaseIndex, 0, 5},
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{"esi", Reg32|BaseIndex, 0, 6},
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{"edi", Reg32|BaseIndex, 0, 7},
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{"r8d", Reg32|BaseIndex, RegRex, 0},
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{"r9d", Reg32|BaseIndex, RegRex, 1},
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{"r10d", Reg32|BaseIndex, RegRex, 2},
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{"r11d", Reg32|BaseIndex, RegRex, 3},
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{"r12d", Reg32|BaseIndex, RegRex, 4},
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{"r13d", Reg32|BaseIndex, RegRex, 5},
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{"r14d", Reg32|BaseIndex, RegRex, 6},
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{"r15d", Reg32|BaseIndex, RegRex, 7},
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{"rax", Reg64|BaseIndex|Acc, 0, 0},
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{"rcx", Reg64|BaseIndex, 0, 1},
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{"rdx", Reg64|BaseIndex, 0, 2},
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{"rbx", Reg64|BaseIndex, 0, 3},
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{"rsp", Reg64, 0, 4},
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{"rbp", Reg64|BaseIndex, 0, 5},
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{"rsi", Reg64|BaseIndex, 0, 6},
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{"rdi", Reg64|BaseIndex, 0, 7},
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{"r8", Reg64|BaseIndex, RegRex, 0},
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{"r9", Reg64|BaseIndex, RegRex, 1},
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{"r10", Reg64|BaseIndex, RegRex, 2},
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{"r11", Reg64|BaseIndex, RegRex, 3},
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{"r12", Reg64|BaseIndex, RegRex, 4},
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{"r13", Reg64|BaseIndex, RegRex, 5},
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{"r14", Reg64|BaseIndex, RegRex, 6},
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{"r15", Reg64|BaseIndex, RegRex, 7},
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/* segment registers */
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{"es", SegReg2, 0, 0},
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{"cs", SegReg2, 0, 1},
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{"ss", SegReg2, 0, 2},
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{"ds", SegReg2, 0, 3},
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{"fs", SegReg3, 0, 4},
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{"gs", SegReg3, 0, 5},
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/* control registers */
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{"cr0", CtrlReg, 0, 0},
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{"cr1", CtrlReg, 0, 1},
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{"cr2", CtrlReg, 0, 2},
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{"cr3", CtrlReg, 0, 3},
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{"cr4", CtrlReg, 0, 4},
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{"cr5", CtrlReg, 0, 5},
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{"cr6", CtrlReg, 0, 6},
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{"cr7", CtrlReg, 0, 7},
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{"cr8", CtrlReg, RegRex, 0},
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{"cr9", CtrlReg, RegRex, 1},
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{"cr10", CtrlReg, RegRex, 2},
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{"cr11", CtrlReg, RegRex, 3},
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{"cr12", CtrlReg, RegRex, 4},
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{"cr13", CtrlReg, RegRex, 5},
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{"cr14", CtrlReg, RegRex, 6},
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{"cr15", CtrlReg, RegRex, 7},
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/* debug registers */
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{"db0", DebugReg, 0, 0},
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{"db1", DebugReg, 0, 1},
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{"db2", DebugReg, 0, 2},
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{"db3", DebugReg, 0, 3},
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{"db4", DebugReg, 0, 4},
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{"db5", DebugReg, 0, 5},
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{"db6", DebugReg, 0, 6},
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{"db7", DebugReg, 0, 7},
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{"db8", DebugReg, RegRex, 0},
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{"db9", DebugReg, RegRex, 1},
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{"db10", DebugReg, RegRex, 2},
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{"db11", DebugReg, RegRex, 3},
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{"db12", DebugReg, RegRex, 4},
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{"db13", DebugReg, RegRex, 5},
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{"db14", DebugReg, RegRex, 6},
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{"db15", DebugReg, RegRex, 7},
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{"dr0", DebugReg, 0, 0},
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{"dr1", DebugReg, 0, 1},
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{"dr2", DebugReg, 0, 2},
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{"dr3", DebugReg, 0, 3},
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{"dr4", DebugReg, 0, 4},
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{"dr5", DebugReg, 0, 5},
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{"dr6", DebugReg, 0, 6},
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{"dr7", DebugReg, 0, 7},
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{"dr8", DebugReg, RegRex, 0},
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{"dr9", DebugReg, RegRex, 1},
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{"dr10", DebugReg, RegRex, 2},
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{"dr11", DebugReg, RegRex, 3},
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{"dr12", DebugReg, RegRex, 4},
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{"dr13", DebugReg, RegRex, 5},
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{"dr14", DebugReg, RegRex, 6},
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{"dr15", DebugReg, RegRex, 7},
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/* test registers */
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{"tr0", TestReg, 0, 0},
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{"tr1", TestReg, 0, 1},
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{"tr2", TestReg, 0, 2},
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{"tr3", TestReg, 0, 3},
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{"tr4", TestReg, 0, 4},
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{"tr5", TestReg, 0, 5},
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{"tr6", TestReg, 0, 6},
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{"tr7", TestReg, 0, 7},
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/* mmx and simd registers */
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{"mm0", MMXReg, 0, 0},
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{"mm1", MMXReg, 0, 1},
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{"mm2", MMXReg, 0, 2},
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{"mm3", MMXReg, 0, 3},
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{"mm4", MMXReg, 0, 4},
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{"mm5", MMXReg, 0, 5},
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{"mm6", MMXReg, 0, 6},
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{"mm7", MMXReg, 0, 7},
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{"xmm0", XMMReg, 0, 0},
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{"xmm1", XMMReg, 0, 1},
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{"xmm2", XMMReg, 0, 2},
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{"xmm3", XMMReg, 0, 3},
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{"xmm4", XMMReg, 0, 4},
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{"xmm5", XMMReg, 0, 5},
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{"xmm6", XMMReg, 0, 6},
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{"xmm7", XMMReg, 0, 7},
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{"xmm8", XMMReg, RegRex, 0},
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{"xmm9", XMMReg, RegRex, 1},
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{"xmm10", XMMReg, RegRex, 2},
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{"xmm11", XMMReg, RegRex, 3},
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{"xmm12", XMMReg, RegRex, 4},
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{"xmm13", XMMReg, RegRex, 5},
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{"xmm14", XMMReg, RegRex, 6},
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{"xmm15", XMMReg, RegRex, 7},
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{"st(0)", FloatReg|FloatAcc, 0, 0},
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{"st(1)", FloatReg, 0, 1},
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{"st(2)", FloatReg, 0, 2},
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{"st(3)", FloatReg, 0, 3},
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{"st(4)", FloatReg, 0, 4},
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{"st(5)", FloatReg, 0, 5},
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{"st(6)", FloatReg, 0, 6},
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{"st(7)", FloatReg, 0, 7},
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{"rip", BaseIndex, 0, 0},
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{NULL, 0, 0, 0}
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