908 lines
21 KiB
C
908 lines
21 KiB
C
/*
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** cpu.c PowerPC cpu-description file
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** (c) in 2002-2017 by Frank Wille
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*/
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#include "vasm.h"
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#include "operands.h"
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mnemonic mnemonics[] = {
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#include "opcodes.h"
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};
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int mnemonic_cnt=sizeof(mnemonics)/sizeof(mnemonics[0]);
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char *cpu_copyright="vasm PowerPC cpu backend 3.0 (c) 2002-2017 Frank Wille";
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char *cpuname = "PowerPC";
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int bitsperbyte = 8;
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int bytespertaddr = 4;
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int ppc_endianess = 1;
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static uint64_t cpu_type = CPU_TYPE_PPC | CPU_TYPE_ALTIVEC | CPU_TYPE_32 | CPU_TYPE_ANY;
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static int regnames = 1;
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static taddr sdreg = 13; /* this is default for V.4, PowerOpen = 2 */
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static taddr sd2reg = 2;
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static unsigned char opt_branch = 0;
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int ppc_data_align(int n)
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{
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if (n<=8) return 1;
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if (n<=16) return 2;
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if (n<=32) return 4;
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return 8;
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}
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int ppc_data_operand(int n)
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{
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if (n&OPSZ_FLOAT) return OPSZ_BITS(n)>32?OP_F64:OP_F32;
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if (OPSZ_BITS(n)<=8) return OP_D8;
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if (OPSZ_BITS(n)<=16) return OP_D16;
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if (OPSZ_BITS(n)<=32) return OP_D32;
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return OP_D64;
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}
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int ppc_operand_optional(operand *op,int type)
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{
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if (powerpc_operands[type].flags & OPER_OPTIONAL) {
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op->attr = REL_NONE;
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op->mode = OPM_NONE;
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op->basereg = NULL;
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op->value = number_expr(0); /* default value 0 */
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if (powerpc_operands[type].flags & OPER_NEXT)
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op->type = NEXT;
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else
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op->type = type;
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return 1;
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}
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else if (powerpc_operands[type].flags & OPER_FAKE) {
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op->type = type;
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op->value = NULL;
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return 1;
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}
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return 0;
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}
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int ppc_available(int idx)
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/* Check if mnemonic is available for selected cpu_type. */
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{
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uint64_t avail = mnemonics[idx].ext.available;
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uint64_t datawidth = CPU_TYPE_32 | CPU_TYPE_64;
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if ((avail & cpu_type) != 0) {
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if ((avail & cpu_type & ~datawidth)!=0 || (cpu_type & CPU_TYPE_ANY)!=0) {
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if (avail & datawidth)
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return (avail & datawidth) == (cpu_type & datawidth)
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|| (cpu_type & CPU_TYPE_64_BRIDGE) != 0;
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else
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return 1;
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}
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}
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return 0;
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}
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static char *parse_reloc_attr(char *p,operand *op)
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{
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p = skip(p);
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while (*p == '@') {
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unsigned char chk;
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p++;
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chk = op->attr;
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if (!strncmp(p,"got",3)) {
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op->attr = REL_GOT;
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p += 3;
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}
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else if (!strncmp(p,"plt",3)) {
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op->attr = REL_PLT;
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p += 3;
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}
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else if (!strncmp(p,"sdax",4)) {
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op->attr = REL_SD;
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p += 4;
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}
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else if (!strncmp(p,"sdarx",5)) {
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op->attr = REL_SD;
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p += 5;
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}
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else if (!strncmp(p,"sdarel",6)) {
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op->attr = REL_SD;
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p += 6;
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}
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else if (!strncmp(p,"sectoff",7)) {
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op->attr = REL_SECOFF;
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p += 7;
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}
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else if (!strncmp(p,"local",5)) {
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op->attr = REL_LOCALPC;
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p += 5;
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}
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else if (!strncmp(p,"globdat",7)) {
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op->attr = REL_GLOBDAT;
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p += 7;
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}
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else if (!strncmp(p,"sda2rel",7)) {
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op->attr = REL_PPCEABI_SDA2;
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p += 7;
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}
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else if (!strncmp(p,"sda21",5)) {
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op->attr = REL_PPCEABI_SDA21;
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p += 5;
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}
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else if (!strncmp(p,"sdai16",6)) {
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op->attr = REL_PPCEABI_SDAI16;
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p += 6;
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}
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else if (!strncmp(p,"sda2i16",7)) {
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op->attr = REL_PPCEABI_SDA2I16;
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p += 7;
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}
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else if (!strncmp(p,"drel",4)) {
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op->attr = REL_MORPHOS_DREL;
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p += 4;
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}
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else if (!strncmp(p,"brel",4)) {
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op->attr = REL_AMIGAOS_BREL;
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p += 4;
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}
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if (chk!=REL_NONE && chk!=op->attr)
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cpu_error(7); /* multiple relocation attributes */
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chk = op->mode;
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if (!strncmp(p,"ha",2)) {
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op->mode = OPM_HA;
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p += 2;
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}
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if (*p == 'h') {
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op->mode = OPM_HI;
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p++;
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}
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if (*p == 'l') {
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op->mode = OPM_LO;
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p++;
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}
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if (chk!=OPM_NONE && chk!=op->mode)
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cpu_error(8); /* multiple hi/lo modifiers */
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}
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return p;
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}
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int parse_operand(char *p,int len,operand *op,int optype)
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/* Parses operands, reads expressions and assigns relocation types. */
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{
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char *start = p;
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int rc = PO_MATCH;
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op->attr = REL_NONE;
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op->mode = OPM_NONE;
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op->basereg = NULL;
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p = skip(p);
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op->value = OP_FLOAT(optype) ? parse_expr_float(&p) : parse_expr(&p);
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if (!OP_DATA(optype)) {
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p = parse_reloc_attr(p,op);
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p = skip(p);
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if (p-start < len && *p=='(') {
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/* parse d(Rn) load/store addressing mode */
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if (powerpc_operands[optype].flags & OPER_PARENS) {
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p++;
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op->basereg = parse_expr(&p);
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p = skip(p);
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if (*p == ')') {
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p = skip(p+1);
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rc = PO_SKIP;
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}
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else {
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cpu_error(5); /* missing closing parenthesis */
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rc = PO_CORRUPT;
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goto leave;
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}
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}
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else {
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cpu_error(4); /* illegal operand type */
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rc = PO_CORRUPT;
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goto leave;
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}
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}
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}
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if (p-start < len)
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cpu_error(3); /* trailing garbage in operand */
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leave:
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op->type = optype;
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return rc;
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}
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static taddr read_sdreg(char **s,taddr def)
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{
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expr *tree;
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taddr val = def;
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*s = skip(*s);
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tree = parse_expr(s);
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simplify_expr(tree);
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if (tree->type==NUM && tree->c.val>=0 && tree->c.val<=31)
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val = tree->c.val;
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else
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cpu_error(13); /* not a valid register */
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free_expr(tree);
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return val;
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}
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char *parse_cpu_special(char *start)
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/* parse cpu-specific directives; return pointer to end of
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cpu-specific text */
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{
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char *name=start,*s=start;
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if (ISIDSTART(*s)) {
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s++;
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while (ISIDCHAR(*s))
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s++;
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if (s-name==6 && !strncmp(name,".sdreg",6)) {
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sdreg = read_sdreg(&s,sdreg);
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return s;
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}
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else if (s-name==7 && !strncmp(name,".sd2reg",7)) {
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sd2reg = read_sdreg(&s,sd2reg);
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return s;
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}
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}
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return start;
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}
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static int get_reloc_type(operand *op)
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{
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int rtype = REL_NONE;
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if (OP_DATA(op->type)) { /* data relocs */
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return REL_ABS;
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}
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else { /* handle instruction relocs */
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const struct powerpc_operand *ppcop = &powerpc_operands[op->type];
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if (ppcop->shift == 0) {
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if (ppcop->bits == 16 || ppcop->bits == 26) {
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if (ppcop->flags & OPER_RELATIVE) { /* a relative branch */
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switch (op->attr) {
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case REL_NONE:
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rtype = REL_PC;
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break;
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case REL_PLT:
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rtype = REL_PLTPC;
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break;
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case REL_LOCALPC:
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rtype = REL_LOCALPC;
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break;
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default:
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cpu_error(11); /* reloc attribute not supported by operand */
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break;
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}
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}
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else if (ppcop->flags & OPER_ABSOLUTE) { /* absolute branch */
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switch (op->attr) {
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case REL_NONE:
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rtype = REL_ABS;
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break;
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case REL_PLT:
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case REL_GLOBDAT:
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case REL_SECOFF:
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rtype = op->attr;
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break;
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default:
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cpu_error(11); /* reloc attribute not supported by operand */
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break;
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}
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}
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else { /* immediate 16 bit or load/store d16(Rn) instruction */
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switch (op->attr) {
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case REL_NONE:
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rtype = REL_ABS;
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break;
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case REL_GOT:
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case REL_PLT:
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case REL_SD:
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case REL_PPCEABI_SDA2:
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case REL_PPCEABI_SDA21:
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case REL_PPCEABI_SDAI16:
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case REL_PPCEABI_SDA2I16:
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case REL_MORPHOS_DREL:
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case REL_AMIGAOS_BREL:
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rtype = op->attr;
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break;
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default:
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cpu_error(11); /* reloc attribute not supported by operand */
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break;
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}
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}
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}
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}
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}
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return rtype;
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}
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static int valid_hiloreloc(int type)
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/* checks if this relocation type allows a @l/@h/@ha modifier */
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{
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switch (type) {
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case REL_ABS:
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case REL_GOT:
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case REL_PLT:
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case REL_MORPHOS_DREL:
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case REL_AMIGAOS_BREL:
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return 1;
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}
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cpu_error(6); /* relocation does not allow hi/lo modifier */
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return 0;
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}
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static taddr make_reloc(int reloctype,operand *op,section *sec,
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taddr pc,rlist **reloclist)
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/* create a reloc-entry when operand contains a non-constant expression */
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{
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taddr val;
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if (!eval_expr(op->value,&val,sec,pc)) {
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/* non-constant expression requires a relocation entry */
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symbol *base;
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int btype,pos,size,offset;
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taddr addend,mask;
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btype = find_base(op->value,&base,sec,pc);
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pos = offset = 0;
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if (btype > BASE_ILLEGAL) {
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if (btype == BASE_PCREL) {
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if (reloctype == REL_ABS)
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reloctype = REL_PC;
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else
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goto illreloc;
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}
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if (op->mode != OPM_NONE) {
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/* check if reloc allows @ha/@h/@l */
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if (!valid_hiloreloc(reloctype))
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op->mode = OPM_NONE;
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}
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if (reloctype == REL_PC && !is_pc_reloc(base,sec)) {
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/* a relative branch - reloc is only needed for external reference */
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return val-pc;
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}
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/* determine reloc size, offset and mask */
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if (OP_DATA(op->type)) { /* data operand */
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switch (op->type) {
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case OP_D8:
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size = 8;
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break;
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case OP_D16:
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size = 16;
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break;
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case OP_D32:
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case OP_F32:
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size = 32;
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break;
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case OP_D64:
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case OP_F64:
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size = 64;
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break;
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default:
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ierror(0);
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break;
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}
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addend = val;
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mask = -1;
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}
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else { /* instruction operand */
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const struct powerpc_operand *ppcop = &powerpc_operands[op->type];
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if (ppcop->flags & (OPER_RELATIVE|OPER_ABSOLUTE)) {
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/* branch instruction */
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if (ppcop->bits == 26) {
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size = 24;
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pos = 6;
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mask = 0x3fffffc;
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}
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else {
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size = 14;
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offset = 2;
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mask = 0xfffc;
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}
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addend = (btype == BASE_PCREL) ? val + offset : val;
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}
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else {
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/* load/store or immediate */
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size = 16;
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offset = 2;
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addend = (btype == BASE_PCREL) ? val + offset : val;
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switch (op->mode) {
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case OPM_LO:
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mask = 0xffff;
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break;
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case OPM_HI:
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mask = 0xffff0000;
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break;
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case OPM_HA:
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add_extnreloc_masked(reloclist,base,addend,reloctype,
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pos,size,offset,0x8000);
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mask = 0xffff0000;
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break;
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default:
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mask = -1;
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break;
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}
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}
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}
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add_extnreloc_masked(reloclist,base,addend,reloctype,
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pos,size,offset,mask);
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}
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else if (btype != BASE_NONE) {
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illreloc:
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general_error(38); /* illegal relocation */
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}
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}
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return val;
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}
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static void fix_reloctype(dblock *db,int rtype)
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{
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rlist *rl;
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for (rl=db->relocs; rl!=NULL; rl=rl->next)
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rl->type = rtype;
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}
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static int cnt_insn_ops(instruction *p)
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{
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int cnt = 0;
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while (cnt<MAX_OPERANDS && p->op[cnt]!=NULL)
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cnt++;
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return cnt;
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}
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static int cnt_mnemo_ops(mnemonic *p)
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{
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int cnt = 0;
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while (cnt<MAX_OPERANDS && p->operand_type[cnt]!=UNUSED)
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cnt++;
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return cnt;
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}
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static void range_check(taddr val,const struct powerpc_operand *o,dblock *db)
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/* checks if a value fits the allowed range for this operand field */
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{
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int32_t v = (int32_t)val;
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int32_t minv = 0;
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int32_t maxv = (1L << o->bits) - 1;
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int force_signopt = 0;
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if (db) {
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if (db->relocs) {
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switch (db->relocs->type) {
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case REL_SD:
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case REL_PPCEABI_SDA2:
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case REL_PPCEABI_SDA21:
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force_signopt = 1; /* relocation allows full positive range */
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break;
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}
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}
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}
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if (o->flags & OPER_SIGNED) {
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minv = ~(maxv >> 1);
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/* @@@ Only recognize this flag in 32-bit mode! Don't care for now */
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if (!(o->flags & OPER_SIGNOPT) && !force_signopt)
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maxv >>= 1;
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}
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if (o->flags & OPER_NEGATIVE)
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v = -v;
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if (v<minv || v>maxv)
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cpu_error(12,v,minv,maxv); /* operand out of range */
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}
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static void negate_bo_cond(uint32_t *p)
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/* negates all conditions in a branch instruction's BO field */
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{
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if (!(*p & 0x02000000))
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*p ^= 0x01000000;
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if (!(*p & 0x00800000))
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*p ^= 0x00400000;
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}
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static uint32_t insertcode(uint32_t i,taddr val,
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const struct powerpc_operand *o)
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{
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if (o->insert) {
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const char *errmsg = NULL;
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i = (o->insert)(i,(int32_t)val,&errmsg);
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if (errmsg)
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cpu_error(0,errmsg);
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}
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else
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i |= ((int32_t)val & ((1<<o->bits)-1)) << o->shift;
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return i;
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}
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size_t eval_operands(instruction *ip,section *sec,taddr pc,
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uint32_t *insn,dblock *db)
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/* evaluate expressions and try to optimize instruction,
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return size of instruction */
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{
|
|
mnemonic *mnemo = &mnemonics[ip->code];
|
|
size_t isize = 4;
|
|
int i,j,omitted;
|
|
operand op;
|
|
|
|
if (insn != NULL)
|
|
*insn = mnemo->ext.opcode;
|
|
|
|
for (i=0; i<MAX_OPERANDS && ip->op[i]!=NULL; i++) {
|
|
const struct powerpc_operand *ppcop;
|
|
int reloctype;
|
|
taddr val;
|
|
|
|
op = *(ip->op[i]);
|
|
|
|
if (op.type == NEXT) {
|
|
/* special case: operand omitted and use this operand's type + 1
|
|
for the next operand */
|
|
op = *(ip->op[++i]);
|
|
op.type = mnemo->operand_type[i-1] + 1;
|
|
}
|
|
|
|
ppcop = &powerpc_operands[op.type];
|
|
|
|
if (ppcop->flags & OPER_FAKE) {
|
|
if (insn != NULL) {
|
|
if (op.value != NULL)
|
|
cpu_error(16); /* ignoring fake operand */
|
|
*insn = insertcode(*insn,0,ppcop);
|
|
}
|
|
continue;
|
|
}
|
|
|
|
if ((reloctype = get_reloc_type(&op)) != REL_NONE) {
|
|
if (db != NULL) {
|
|
val = make_reloc(reloctype,&op,sec,pc,&db->relocs);
|
|
}
|
|
else {
|
|
if (!eval_expr(op.value,&val,sec,pc)) {
|
|
if (reloctype == REL_PC)
|
|
val -= pc;
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
if (!eval_expr(op.value,&val,sec,pc))
|
|
if (insn != NULL)
|
|
cpu_error(2); /* constant integer expression required */
|
|
}
|
|
|
|
/* execute modifier on val */
|
|
if (op.mode) {
|
|
switch (op.mode) {
|
|
case OPM_LO:
|
|
val &= 0xffff;
|
|
break;
|
|
case OPM_HI:
|
|
val = (val>>16) & 0xffff;
|
|
break;
|
|
case OPM_HA:
|
|
val = ((val>>16) + ((val & 0x8000) ? 1 : 0) & 0xffff);
|
|
break;
|
|
}
|
|
if ((ppcop->flags & OPER_SIGNED) && (val & 0x8000))
|
|
val -= 0x10000;
|
|
}
|
|
|
|
/* do optimizations here: */
|
|
|
|
if (opt_branch) {
|
|
if (reloctype==REL_PC &&
|
|
(op.type==BD || op.type==BDM || op.type==BDP)) {
|
|
if (val<-0x8000 || val>0x7fff) {
|
|
/* "B<cc>" branch destination out of range, convert into
|
|
a "B<!cc> ; B" combination */
|
|
if (insn != NULL) {
|
|
negate_bo_cond(insn);
|
|
*insn = insertcode(*insn,8,ppcop); /* B<!cc> $+8 */
|
|
insn++;
|
|
*insn = B(18,0,0); /* set B instruction opcode */
|
|
val -= 4;
|
|
}
|
|
ppcop = &powerpc_operands[LI]; /* set oper. for B instruction */
|
|
isize = 8;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (ppcop->flags & OPER_PARENS) {
|
|
if (op.basereg) {
|
|
/* a load/store instruction d(Rn) carries basereg in current op */
|
|
taddr reg;
|
|
|
|
if (db!=NULL && op.mode==OPM_NONE && op.attr==REL_NONE) {
|
|
if (eval_expr(op.basereg,®,sec,pc)) {
|
|
if (reg == sdreg) /* is it a small data reference? */
|
|
fix_reloctype(db,REL_SD);
|
|
else if (reg == sd2reg) /* EABI small data 2 */
|
|
fix_reloctype(db,REL_PPCEABI_SDA2);
|
|
}
|
|
}
|
|
|
|
/* write displacement */
|
|
if (insn != NULL) {
|
|
range_check(val,ppcop,db);
|
|
*insn = insertcode(*insn,val,ppcop);
|
|
}
|
|
|
|
/* move to next operand type to handle base register */
|
|
op.type = mnemo->operand_type[++i];
|
|
ppcop = &powerpc_operands[op.type];
|
|
op.attr = REL_NONE;
|
|
op.mode = OPM_NONE;
|
|
op.value = op.basereg;
|
|
if (!eval_expr(op.value,&val,sec,pc))
|
|
if (insn != NULL)
|
|
cpu_error(2); /* constant integer expression required */
|
|
}
|
|
else if (insn != NULL)
|
|
cpu_error(14); /* missing base register */
|
|
}
|
|
|
|
/* write val (register, immediate, etc.) */
|
|
if (insn != NULL) {
|
|
range_check(val,ppcop,db);
|
|
*insn = insertcode(*insn,val,ppcop);
|
|
}
|
|
}
|
|
|
|
return isize;
|
|
}
|
|
|
|
|
|
size_t instruction_size(instruction *ip,section *sec,taddr pc)
|
|
/* Calculate the size of the current instruction; must be identical
|
|
to the data created by eval_instruction. */
|
|
{
|
|
/* determine optimized size, when needed */
|
|
if (opt_branch)
|
|
return eval_operands(ip,sec,pc,NULL,NULL);
|
|
|
|
/* otherwise an instruction is always 4 bytes */
|
|
return 4;
|
|
}
|
|
|
|
|
|
dblock *eval_instruction(instruction *ip,section *sec,taddr pc)
|
|
/* Convert an instruction into a DATA atom including relocations,
|
|
when necessary. */
|
|
{
|
|
dblock *db = new_dblock();
|
|
uint32_t insn[2];
|
|
|
|
if (db->size = eval_operands(ip,sec,pc,insn,db)) {
|
|
unsigned char *d = db->data = mymalloc(db->size);
|
|
int i;
|
|
|
|
for (i=0; i<db->size/4; i++)
|
|
d = setval(1,d,4,insn[i]);
|
|
}
|
|
|
|
return db;
|
|
}
|
|
|
|
|
|
dblock *eval_data(operand *op,size_t bitsize,section *sec,taddr pc)
|
|
/* Create a dblock (with relocs, if necessary) for size bits of data. */
|
|
{
|
|
dblock *db = new_dblock();
|
|
taddr val;
|
|
tfloat flt;
|
|
|
|
if ((bitsize & 7) || bitsize > 64)
|
|
cpu_error(9,bitsize); /* data size not supported */
|
|
if (!OP_DATA(op->type))
|
|
ierror(0);
|
|
|
|
db->size = bitsize >> 3;
|
|
db->data = mymalloc(db->size);
|
|
|
|
if (type_of_expr(op->value) == FLT) {
|
|
if (!eval_expr_float(op->value,&flt))
|
|
general_error(60); /* cannot evaluate floating point */
|
|
|
|
switch (bitsize) {
|
|
case 32:
|
|
conv2ieee32(1,db->data,flt);
|
|
break;
|
|
case 64:
|
|
conv2ieee64(1,db->data,flt);
|
|
break;
|
|
default:
|
|
cpu_error(10); /* data has illegal type */
|
|
break;
|
|
}
|
|
}
|
|
else {
|
|
val = make_reloc(get_reloc_type(op),op,sec,pc,&db->relocs);
|
|
|
|
switch (db->size) {
|
|
case 1:
|
|
db->data[0] = val & 0xff;
|
|
break;
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
setval(ppc_endianess,db->data,db->size,val);
|
|
break;
|
|
default:
|
|
ierror(0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return db;
|
|
}
|
|
|
|
|
|
operand *new_operand()
|
|
{
|
|
operand *new = mymalloc(sizeof(*new));
|
|
new->type = -1;
|
|
new->mode = OPM_NONE;
|
|
return new;
|
|
}
|
|
|
|
|
|
static void define_regnames(void)
|
|
{
|
|
char r[4];
|
|
int i;
|
|
|
|
for (i=0; i<32; i++) {
|
|
sprintf(r,"r%d",i);
|
|
set_internal_abs(r,(taddr)i);
|
|
r[0] = 'f';
|
|
set_internal_abs(r,(taddr)i);
|
|
r[0] = 'v';
|
|
set_internal_abs(r,(taddr)i);
|
|
}
|
|
for (i=0; i<8; i++) {
|
|
sprintf(r,"cr%d",i);
|
|
set_internal_abs(r,(taddr)i);
|
|
}
|
|
set_internal_abs("vrsave",256);
|
|
set_internal_abs("lt",0);
|
|
set_internal_abs("gt",1);
|
|
set_internal_abs("eq",2);
|
|
set_internal_abs("so",3);
|
|
set_internal_abs("un",3);
|
|
set_internal_abs("sp",1);
|
|
set_internal_abs("rtoc",2);
|
|
set_internal_abs("fp",31);
|
|
set_internal_abs("fpscr",0);
|
|
set_internal_abs("xer",1);
|
|
set_internal_abs("lr",8);
|
|
set_internal_abs("ctr",9);
|
|
}
|
|
|
|
|
|
int init_cpu()
|
|
{
|
|
if (regnames)
|
|
define_regnames();
|
|
return 1;
|
|
}
|
|
|
|
|
|
int cpu_args(char *p)
|
|
{
|
|
int i;
|
|
|
|
if (!strncmp(p,"-m",2)) {
|
|
p += 2;
|
|
if (!strcmp(p,"pwrx") || !strcmp(p,"pwr2"))
|
|
cpu_type = CPU_TYPE_POWER | CPU_TYPE_POWER2 | CPU_TYPE_32;
|
|
else if (!strcmp(p,"pwr"))
|
|
cpu_type = CPU_TYPE_POWER | CPU_TYPE_32;
|
|
else if (!strcmp(p,"601"))
|
|
cpu_type = CPU_TYPE_601 | CPU_TYPE_PPC | CPU_TYPE_32;
|
|
else if (!strcmp(p,"ppc") || !strcmp(p,"ppc32") || !strncmp(p,"60",2) ||
|
|
!strncmp(p,"75",2) || !strncmp(p,"85",2))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_32;
|
|
else if (!strcmp(p,"ppc64") || !strcmp(p,"620"))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_64;
|
|
else if (!strcmp(p,"7450"))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_7450 | CPU_TYPE_32 | CPU_TYPE_ALTIVEC;
|
|
else if (!strncmp(p,"74",2) || !strcmp(p,"avec") || !strcmp(p,"altivec"))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_32 | CPU_TYPE_ALTIVEC;
|
|
else if (!strcmp(p,"403"))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_403 | CPU_TYPE_32;
|
|
else if (!strcmp(p,"405"))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_403 | CPU_TYPE_405 | CPU_TYPE_32;
|
|
else if (!strncmp(p,"44",2) || !strncmp(p,"46",2))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_440 | CPU_TYPE_BOOKE | CPU_TYPE_ISEL
|
|
| CPU_TYPE_RFMCI | CPU_TYPE_32;
|
|
else if (!strcmp(p,"821") || !strcmp(p,"850") || !strcmp(p,"860"))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_860 | CPU_TYPE_32;
|
|
else if (!strcmp(p,"e300"))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_E300 | CPU_TYPE_32;
|
|
else if (!strcmp(p,"e500"))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_E500 | CPU_TYPE_BOOKE | CPU_TYPE_ISEL
|
|
| CPU_TYPE_SPE | CPU_TYPE_EFS | CPU_TYPE_PMR | CPU_TYPE_RFMCI
|
|
| CPU_TYPE_32;
|
|
else if (!strcmp(p,"booke"))
|
|
cpu_type = CPU_TYPE_PPC | CPU_TYPE_BOOKE;
|
|
else if (!strcmp(p,"com"))
|
|
cpu_type = CPU_TYPE_COMMON | CPU_TYPE_32;
|
|
else if (!strcmp(p,"any"))
|
|
cpu_type |= CPU_TYPE_ANY;
|
|
else
|
|
return 0;
|
|
}
|
|
else if (!strcmp(p,"-no-regnames"))
|
|
regnames = 0;
|
|
else if (!strcmp(p,"-little"))
|
|
ppc_endianess = 0;
|
|
else if (!strcmp(p,"-big"))
|
|
ppc_endianess = 1;
|
|
else if (!strncmp(p,"-sdreg=",7)) {
|
|
i = atoi(p+7);
|
|
if (i>=0 && i<=31)
|
|
sdreg = i;
|
|
else
|
|
cpu_error(13); /* not a valid register */
|
|
}
|
|
else if (!strncmp(p,"-sd2reg=",8)) {
|
|
i = atoi(p+8);
|
|
if (i>=0 && i<=31)
|
|
sd2reg = i;
|
|
else
|
|
cpu_error(13); /* not a valid register */
|
|
}
|
|
else if (!strcmp(p,"-opt-branch"))
|
|
opt_branch = 1;
|
|
else
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|