86 lines
2 KiB
Text
86 lines
2 KiB
Text
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This chapter documents the backend for the Motorola 6800
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microprocessor family.
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@section Legal
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This module is written in 2013-2016 by Esben Norby and Frank Wille
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and is covered by the vasm copyright without modifications.
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@section Additional options for this module
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This module provides the following additional options:
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@table @option
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@item -m6800
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Generate code for the 6800 CPU (default setting).
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@item -m6801
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Generate code for the 6801 CPU.
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@item -m68hc11
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Generate code for the 68HC11 CPU.
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@end table
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@section General
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This backend accepts 6800 family instructions for the following CPUs:
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@itemize
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@item 6800 code generation: 6800, 6802, 6808.
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@item 6801 code generation: 6801, 6803.
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@item 68HC11.
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@end itemize
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The 6804, 6805, 68HC08 and 6809 are not supported, they use a similar
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instruction set, but are not opcode compatible.
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The target address type is 16 bit.
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Instructions consist of one up to five bytes and require no alignment.
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There is also no alignment requirement for sections and data.
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@section Extensions
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This backend provides the following specific extensions:
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@itemize @minus
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@item When an instruction supports direct and extended addressing mode
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the @code{<} character can be used to force direct mode and the
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@code{>} character forces extended mode. Otherwise the assembler selects
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the best mode automatically, which defaults to extended mode for external
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symbols.
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@item When applying the operation @code{/256}, @code{%256} or @code{&256}
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on a label, an appropriate lo/hi-byte relocation will automatically be
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generated.
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@end itemize
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@section Optimizations
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None.
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@section Known Problems
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Some known problems of this module at the moment:
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@itemize @minus
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@item None?
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@end itemize
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@section Error Messages
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This module has the following error messages:
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@itemize @minus
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@item 2001: data size %d not supported
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@item 2002: operand doesn't fit into 8-bits
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@item 2003: branch destination out of range
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@end itemize
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