1042 lines
51 KiB
C
1042 lines
51 KiB
C
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"mov",OP_SREG,OP_SREG,0,0,EN_ARITHR16,0,CPU_ALL,
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||
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"mov",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,0,CPU_ALL,
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||
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"mov",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,0,CPU_ALL,
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||
|
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"mov",OP_REG,OP_REG,0,0,EN_ARITHR32,0,CPU_ALL,
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||
|
|
"mov",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,0,CPU_ALL,
|
||
|
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"mov",OP_REG,OP_IMM5,0,0,EN_ARITHI32,0,CPU_ALL,
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"mov",OP_REG,OP_IMM32,0,0,EN_ARITHI48,0,CPU_ALL,
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"cmn",OP_SREG,OP_SREG,0,0,EN_ARITHR16,1,CPU_ALL,
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||
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"cmn",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,1,CPU_ALL,
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||
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"cmn",OP_REG,OP_REG,0,0,EN_ARITHR32,1,CPU_ALL,
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||
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"cmn",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,1,CPU_ALL,
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||
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"cmn",OP_REG,OP_IMM5,0,0,EN_ARITHI32,1,CPU_ALL,
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||
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"cmn",OP_REG,OP_IMM32,0,0,EN_ARITHI48,1,CPU_ALL,
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"add",OP_SREG,OP_SREG,0,0,EN_ARITHR16,2,CPU_ALL,
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||
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"add",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,2,CPU_ALL,
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||
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"add",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,2,CPU_ALL,
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||
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"add",OP_REG,OP_REG,0,0,EN_ARITHR32,2,CPU_ALL,
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||
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"add",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,2,CPU_ALL,
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||
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"add",OP_REG,OP_IMM5,0,0,EN_ARITHI32,2,CPU_ALL,
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||
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"add",OP_REG,OP_IMM32,0,0,EN_ARITHI48,2,CPU_ALL,
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"add",OP_REG,OP_REG,OP_IMM32,0,EN_ADD48,2,CPU_ALL,
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"bic",OP_SREG,OP_SREG,0,0,EN_ARITHR16,3,CPU_ALL,
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"bic",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,3,CPU_ALL,
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||
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"bic",OP_REG,OP_REG,0,0,EN_ARITHR32,3,CPU_ALL,
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"bic",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,3,CPU_ALL,
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"bic",OP_REG,OP_IMM5,0,0,EN_ARITHI32,3,CPU_ALL,
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"bic",OP_REG,OP_IMM32,0,0,EN_ARITHI48,3,CPU_ALL,
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"mul",OP_SREG,OP_SREG,0,0,EN_ARITHR16,4,CPU_ALL,
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"mul",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,4,CPU_ALL,
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"mul",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,4,CPU_ALL,
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"mul",OP_REG,OP_REG,0,0,EN_ARITHR32,4,CPU_ALL,
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"mul",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,4,CPU_ALL,
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"mul",OP_REG,OP_IMM5,0,0,EN_ARITHI32,4,CPU_ALL,
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"mul",OP_REG,OP_IMM32,0,0,EN_ARITHI48,4,CPU_ALL,
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"eor",OP_SREG,OP_SREG,0,0,EN_ARITHR16,5,CPU_ALL,
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"eor",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,5,CPU_ALL,
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"eor",OP_REG,OP_REG,0,0,EN_ARITHR32,5,CPU_ALL,
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"eor",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,5,CPU_ALL,
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"eor",OP_REG,OP_IMM5,0,0,EN_ARITHI32,5,CPU_ALL,
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"eor",OP_REG,OP_IMM32,0,0,EN_ARITHI48,5,CPU_ALL,
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"sub",OP_SREG,OP_SREG,0,0,EN_ARITHR16,6,CPU_ALL,
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"sub",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,6,CPU_ALL,
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"sub",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,6,CPU_ALL,
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"sub",OP_REG,OP_REG,0,0,EN_ARITHR32,6,CPU_ALL,
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"sub",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,6,CPU_ALL,
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"sub",OP_REG,OP_IMM5,0,0,EN_ARITHI32,6,CPU_ALL,
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"sub",OP_REG,OP_IMM32,0,0,EN_ARITHI48,6,CPU_ALL,
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"sub",OP_REG,OP_REG,OP_IMM32,0,EN_ADD48,6,CPU_ALL,
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"and",OP_SREG,OP_SREG,0,0,EN_ARITHR16,7,CPU_ALL,
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"and",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,7,CPU_ALL,
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"and",OP_REG,OP_REG,0,0,EN_ARITHR32,7,CPU_ALL,
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"and",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,7,CPU_ALL,
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"and",OP_REG,OP_IMM5,0,0,EN_ARITHI32,7,CPU_ALL,
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"and",OP_REG,OP_IMM32,0,0,EN_ARITHI48,7,CPU_ALL,
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"mvn",OP_SREG,OP_SREG,0,0,EN_ARITHR16,8,CPU_ALL,
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"mvn",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,8,CPU_ALL,
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"mvn",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,8,CPU_ALL,
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"mvn",OP_REG,OP_REG,0,0,EN_ARITHR32,8,CPU_ALL,
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"mvn",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,8,CPU_ALL,
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"mvn",OP_REG,OP_IMM5,0,0,EN_ARITHI32,8,CPU_ALL,
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"mvn",OP_REG,OP_IMM32,0,0,EN_ARITHI48,8,CPU_ALL,
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// Alternate name
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"not",OP_SREG,OP_SREG,0,0,EN_ARITHR16,8,CPU_ALL,
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"not",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,8,CPU_ALL,
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"not",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,8,CPU_ALL,
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"not",OP_REG,OP_REG,0,0,EN_ARITHR32,8,CPU_ALL,
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"not",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,8,CPU_ALL,
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"not",OP_REG,OP_IMM5,0,0,EN_ARITHI32,8,CPU_ALL,
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"not",OP_REG,OP_IMM32,0,0,EN_ARITHI48,8,CPU_ALL,
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"ror",OP_SREG,OP_SREG,0,0,EN_ARITHR16,9,CPU_ALL,
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"ror",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,9,CPU_ALL,
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"ror",OP_REG,OP_REG,0,0,EN_ARITHR32,9,CPU_ALL,
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"ror",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,9,CPU_ALL,
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"ror",OP_REG,OP_IMM5,0,0,EN_ARITHI32,9,CPU_ALL,
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"ror",OP_REG,OP_IMM32,0,0,EN_ARITHI48,9,CPU_ALL,
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"cmp",OP_SREG,OP_SREG,0,0,EN_ARITHR16,10,CPU_ALL,
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"cmp",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,10,CPU_ALL,
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"cmp",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,10,CPU_ALL,
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"cmp",OP_REG,OP_REG,0,0,EN_ARITHR32,10,CPU_ALL,
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"cmp",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,10,CPU_ALL,
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"cmp",OP_REG,OP_IMM5,0,0,EN_ARITHI32,10,CPU_ALL,
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"cmp",OP_REG,OP_IMM32,0,0,EN_ARITHI48,10,CPU_ALL,
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"rsb",OP_SREG,OP_SREG,0,0,EN_ARITHR16,11,CPU_ALL,
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"rsb",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,11,CPU_ALL,
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"rsb",OP_REG,OP_REG,0,0,EN_ARITHR32,11,CPU_ALL,
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"rsb",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,11,CPU_ALL,
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"rsb",OP_REG,OP_IMM5,0,0,EN_ARITHI32,11,CPU_ALL,
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"rsb",OP_REG,OP_IMM32,0,0,EN_ARITHI48,11,CPU_ALL,
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"btst",OP_SREG,OP_SREG,0,0,EN_ARITHR16,12,CPU_ALL,
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"btst",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,12,CPU_ALL,
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"btst",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,12,CPU_ALL,
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"btst",OP_REG,OP_REG,0,0,EN_ARITHR32,12,CPU_ALL,
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"btst",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,12,CPU_ALL,
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"btst",OP_REG,OP_IMM5,0,0,EN_ARITHI32,12,CPU_ALL,
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"btst",OP_REG,OP_IMM32,0,0,EN_ARITHI48,12,CPU_ALL,
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"or",OP_SREG,OP_SREG,0,0,EN_ARITHR16,13,CPU_ALL,
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"or",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,13,CPU_ALL,
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"or",OP_REG,OP_REG,0,0,EN_ARITHR32,13,CPU_ALL,
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"or",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,13,CPU_ALL,
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"or",OP_REG,OP_IMM5,0,0,EN_ARITHI32,13,CPU_ALL,
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"or",OP_REG,OP_IMM32,0,0,EN_ARITHI48,13,CPU_ALL,
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"extu",OP_SREG,OP_SREG,0,0,EN_ARITHR16,14,CPU_ALL,
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"extu",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,14,CPU_ALL,
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"extu",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,14,CPU_ALL,
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"extu",OP_REG,OP_REG,0,0,EN_ARITHR32,14,CPU_ALL,
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"extu",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,14,CPU_ALL,
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"extu",OP_REG,OP_IMM5,0,0,EN_ARITHI32,14,CPU_ALL,
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"extu",OP_REG,OP_IMM32,0,0,EN_ARITHI48,14,CPU_ALL,
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"max",OP_SREG,OP_SREG,0,0,EN_ARITHR16,15,CPU_ALL,
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"max",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,15,CPU_ALL,
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"max",OP_REG,OP_REG,0,0,EN_ARITHR32,15,CPU_ALL,
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"max",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,15,CPU_ALL,
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"max",OP_REG,OP_IMM5,0,0,EN_ARITHI32,15,CPU_ALL,
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"max",OP_REG,OP_IMM32,0,0,EN_ARITHI48,15,CPU_ALL,
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"bset",OP_SREG,OP_SREG,0,0,EN_ARITHR16,16,CPU_ALL,
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"bset",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,16,CPU_ALL,
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"bset",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,16,CPU_ALL,
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"bset",OP_REG,OP_REG,0,0,EN_ARITHR32,16,CPU_ALL,
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"bset",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,16,CPU_ALL,
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"bset",OP_REG,OP_IMM5,0,0,EN_ARITHI32,16,CPU_ALL,
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"bset",OP_REG,OP_IMM32,0,0,EN_ARITHI48,16,CPU_ALL,
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"min",OP_SREG,OP_SREG,0,0,EN_ARITHR16,17,CPU_ALL,
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"min",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,17,CPU_ALL,
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"min",OP_REG,OP_REG,0,0,EN_ARITHR32,17,CPU_ALL,
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"min",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,17,CPU_ALL,
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"min",OP_REG,OP_IMM5,0,0,EN_ARITHI32,17,CPU_ALL,
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"min",OP_REG,OP_IMM32,0,0,EN_ARITHI48,17,CPU_ALL,
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"bclr",OP_SREG,OP_SREG,0,0,EN_ARITHR16,18,CPU_ALL,
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"bclr",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,18,CPU_ALL,
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"bclr",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,18,CPU_ALL,
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"bclr",OP_REG,OP_REG,0,0,EN_ARITHR32,18,CPU_ALL,
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"bclr",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,18,CPU_ALL,
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"bclr",OP_REG,OP_IMM5,0,0,EN_ARITHI32,18,CPU_ALL,
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"bclr",OP_REG,OP_IMM32,0,0,EN_ARITHI48,18,CPU_ALL,
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"adds2",OP_SREG,OP_SREG,0,0,EN_ARITHR16,19,CPU_ALL,
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"adds2",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,19,CPU_ALL,
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"adds2",OP_REG,OP_REG,0,0,EN_ARITHR32,19,CPU_ALL,
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"adds2",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,19,CPU_ALL,
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"adds2",OP_REG,OP_IMM5,0,0,EN_ARITHI32,19,CPU_ALL,
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"adds2",OP_REG,OP_IMM32,0,0,EN_ARITHI48,19,CPU_ALL,
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// Alternate name
|
||
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"addscale2",OP_SREG,OP_SREG,0,0,EN_ARITHR16,19,CPU_ALL,
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||
|
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"addscale2",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,19,CPU_ALL,
|
||
|
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"addscale2",OP_REG,OP_REG,0,0,EN_ARITHR32,19,CPU_ALL,
|
||
|
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"addscale2",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,19,CPU_ALL,
|
||
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"addscale2",OP_REG,OP_IMM5,0,0,EN_ARITHI32,19,CPU_ALL,
|
||
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"addscale2",OP_REG,OP_IMM32,0,0,EN_ARITHI48,19,CPU_ALL,
|
||
|
|
|
||
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"bchg",OP_SREG,OP_SREG,0,0,EN_ARITHR16,20,CPU_ALL,
|
||
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"bchg",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,20,CPU_ALL,
|
||
|
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"bchg",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,20,CPU_ALL,
|
||
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"bchg",OP_REG,OP_REG,0,0,EN_ARITHR32,20,CPU_ALL,
|
||
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"bchg",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,20,CPU_ALL,
|
||
|
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"bchg",OP_REG,OP_IMM5,0,0,EN_ARITHI32,20,CPU_ALL,
|
||
|
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"bchg",OP_REG,OP_IMM32,0,0,EN_ARITHI48,20,CPU_ALL,
|
||
|
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|
||
|
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"adds4",OP_SREG,OP_SREG,0,0,EN_ARITHR16,21,CPU_ALL,
|
||
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"adds4",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,21,CPU_ALL,
|
||
|
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"adds4",OP_REG,OP_REG,0,0,EN_ARITHR32,21,CPU_ALL,
|
||
|
|
"adds4",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,21,CPU_ALL,
|
||
|
|
"adds4",OP_REG,OP_IMM5,0,0,EN_ARITHI32,21,CPU_ALL,
|
||
|
|
"adds4",OP_REG,OP_IMM32,0,0,EN_ARITHI48,21,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
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"addscale4",OP_SREG,OP_SREG,0,0,EN_ARITHR16,21,CPU_ALL,
|
||
|
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"addscale4",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,21,CPU_ALL,
|
||
|
|
"addscale4",OP_REG,OP_REG,0,0,EN_ARITHR32,21,CPU_ALL,
|
||
|
|
"addscale4",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,21,CPU_ALL,
|
||
|
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"addscale4",OP_REG,OP_IMM5,0,0,EN_ARITHI32,21,CPU_ALL,
|
||
|
|
"addscale4",OP_REG,OP_IMM32,0,0,EN_ARITHI48,21,CPU_ALL,
|
||
|
|
|
||
|
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"adds8",OP_SREG,OP_SREG,0,0,EN_ARITHR16,22,CPU_ALL,
|
||
|
|
"adds8",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,22,CPU_ALL,
|
||
|
|
"adds8",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,22,CPU_ALL,
|
||
|
|
"adds8",OP_REG,OP_REG,0,0,EN_ARITHR32,22,CPU_ALL,
|
||
|
|
"adds8",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,22,CPU_ALL,
|
||
|
|
"adds8",OP_REG,OP_IMM5,0,0,EN_ARITHI32,22,CPU_ALL,
|
||
|
|
"adds8",OP_REG,OP_IMM32,0,0,EN_ARITHI48,22,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"addscale8",OP_SREG,OP_SREG,0,0,EN_ARITHR16,22,CPU_ALL,
|
||
|
|
"addscale8",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,22,CPU_ALL,
|
||
|
|
"addscale8",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,22,CPU_ALL,
|
||
|
|
"addscale8",OP_REG,OP_REG,0,0,EN_ARITHR32,22,CPU_ALL,
|
||
|
|
"addscale8",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,22,CPU_ALL,
|
||
|
|
"addscale8",OP_REG,OP_IMM5,0,0,EN_ARITHI32,22,CPU_ALL,
|
||
|
|
"addscale8",OP_REG,OP_IMM32,0,0,EN_ARITHI48,22,CPU_ALL,
|
||
|
|
|
||
|
|
"adds16",OP_SREG,OP_SREG,0,0,EN_ARITHR16,23,CPU_ALL,
|
||
|
|
"adds16",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,23,CPU_ALL,
|
||
|
|
"adds16",OP_REG,OP_REG,0,0,EN_ARITHR32,23,CPU_ALL,
|
||
|
|
"adds16",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,23,CPU_ALL,
|
||
|
|
"adds16",OP_REG,OP_IMM5,0,0,EN_ARITHI32,23,CPU_ALL,
|
||
|
|
"adds16",OP_REG,OP_IMM32,0,0,EN_ARITHI48,23,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"addscale16",OP_SREG,OP_SREG,0,0,EN_ARITHR16,23,CPU_ALL,
|
||
|
|
"addscale16",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,23,CPU_ALL,
|
||
|
|
"addscale16",OP_REG,OP_REG,0,0,EN_ARITHR32,23,CPU_ALL,
|
||
|
|
"addscale16",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,23,CPU_ALL,
|
||
|
|
"addscale16",OP_REG,OP_IMM5,0,0,EN_ARITHI32,23,CPU_ALL,
|
||
|
|
"addscale16",OP_REG,OP_IMM32,0,0,EN_ARITHI48,23,CPU_ALL,
|
||
|
|
|
||
|
|
"exts",OP_SREG,OP_SREG,0,0,EN_ARITHR16,24,CPU_ALL,
|
||
|
|
"exts",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,24,CPU_ALL,
|
||
|
|
"exts",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,24,CPU_ALL,
|
||
|
|
"exts",OP_REG,OP_REG,0,0,EN_ARITHR32,24,CPU_ALL,
|
||
|
|
"exts",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,24,CPU_ALL,
|
||
|
|
"exts",OP_REG,OP_IMM5,0,0,EN_ARITHI32,24,CPU_ALL,
|
||
|
|
"exts",OP_REG,OP_IMM32,0,0,EN_ARITHI48,24,CPU_ALL,
|
||
|
|
|
||
|
|
"neg",OP_SREG,OP_SREG,0,0,EN_ARITHR16,25,CPU_ALL,
|
||
|
|
"neg",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,25,CPU_ALL,
|
||
|
|
"neg",OP_REG,OP_REG,0,0,EN_ARITHR32,25,CPU_ALL,
|
||
|
|
"neg",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,25,CPU_ALL,
|
||
|
|
"neg",OP_REG,OP_IMM5,0,0,EN_ARITHI32,25,CPU_ALL,
|
||
|
|
"neg",OP_REG,OP_IMM32,0,0,EN_ARITHI48,25,CPU_ALL,
|
||
|
|
|
||
|
|
"lsr",OP_SREG,OP_SREG,0,0,EN_ARITHR16,26,CPU_ALL,
|
||
|
|
"lsr",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,26,CPU_ALL,
|
||
|
|
"lsr",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,26,CPU_ALL,
|
||
|
|
"lsr",OP_REG,OP_REG,0,0,EN_ARITHR32,26,CPU_ALL,
|
||
|
|
"lsr",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,26,CPU_ALL,
|
||
|
|
"lsr",OP_REG,OP_IMM5,0,0,EN_ARITHI32,26,CPU_ALL,
|
||
|
|
"lsr",OP_REG,OP_IMM32,0,0,EN_ARITHI48,26,CPU_ALL,
|
||
|
|
|
||
|
|
"clz",OP_SREG,OP_SREG,0,0,EN_ARITHR16,27,CPU_ALL,
|
||
|
|
"clz",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,27,CPU_ALL,
|
||
|
|
"clz",OP_REG,OP_REG,0,0,EN_ARITHR32,27,CPU_ALL,
|
||
|
|
"clz",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,27,CPU_ALL,
|
||
|
|
"clz",OP_REG,OP_IMM5,0,0,EN_ARITHI32,27,CPU_ALL,
|
||
|
|
"clz",OP_REG,OP_IMM32,0,0,EN_ARITHI48,27,CPU_ALL,
|
||
|
|
|
||
|
|
"lsl",OP_SREG,OP_SREG,0,0,EN_ARITHR16,28,CPU_ALL,
|
||
|
|
"lsl",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,28,CPU_ALL,
|
||
|
|
"lsl",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,28,CPU_ALL,
|
||
|
|
"lsl",OP_REG,OP_REG,0,0,EN_ARITHR32,28,CPU_ALL,
|
||
|
|
"lsl",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,28,CPU_ALL,
|
||
|
|
"lsl",OP_REG,OP_IMM5,0,0,EN_ARITHI32,28,CPU_ALL,
|
||
|
|
"lsl",OP_REG,OP_IMM32,0,0,EN_ARITHI48,28,CPU_ALL,
|
||
|
|
|
||
|
|
"brev",OP_SREG,OP_SREG,0,0,EN_ARITHR16,29,CPU_ALL,
|
||
|
|
"brev",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,29,CPU_ALL,
|
||
|
|
"brev",OP_REG,OP_REG,0,0,EN_ARITHR32,29,CPU_ALL,
|
||
|
|
"brev",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,29,CPU_ALL,
|
||
|
|
"brev",OP_REG,OP_IMM5,0,0,EN_ARITHI32,29,CPU_ALL,
|
||
|
|
"brev",OP_REG,OP_IMM32,0,0,EN_ARITHI48,29,CPU_ALL,
|
||
|
|
|
||
|
|
"asr",OP_SREG,OP_SREG,0,0,EN_ARITHR16,30,CPU_ALL,
|
||
|
|
"asr",OP_SREG,OP_IMM5,0,0,EN_ARITHI16,30,CPU_ALL,
|
||
|
|
"asr",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,30,CPU_ALL,
|
||
|
|
"asr",OP_REG,OP_REG,0,0,EN_ARITHR32,30,CPU_ALL,
|
||
|
|
"asr",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,30,CPU_ALL,
|
||
|
|
"asr",OP_REG,OP_IMM5,0,0,EN_ARITHI32,30,CPU_ALL,
|
||
|
|
"asr",OP_REG,OP_IMM32,0,0,EN_ARITHI48,30,CPU_ALL,
|
||
|
|
|
||
|
|
"abs",OP_SREG,OP_SREG,0,0,EN_ARITHR16,31,CPU_ALL,
|
||
|
|
"abs",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,31,CPU_ALL,
|
||
|
|
"abs",OP_REG,OP_REG,0,0,EN_ARITHR32,31,CPU_ALL,
|
||
|
|
"abs",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,31,CPU_ALL,
|
||
|
|
"abs",OP_REG,OP_IMM5,0,0,EN_ARITHI32,31,CPU_ALL,
|
||
|
|
"abs",OP_REG,OP_IMM32,0,0,EN_ARITHI48,31,CPU_ALL,
|
||
|
|
|
||
|
|
"mulhds",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,32,CPU_ALL,
|
||
|
|
"mulhds",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,32,CPU_ALL,
|
||
|
|
"mulhdsu",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,33,CPU_ALL,
|
||
|
|
"mulhdsu",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,33,CPU_ALL,
|
||
|
|
"mulhdus",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,34,CPU_ALL,
|
||
|
|
"mulhdus",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,34,CPU_ALL,
|
||
|
|
"mulhdu",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,35,CPU_ALL,
|
||
|
|
"mulhdu",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,35,CPU_ALL,
|
||
|
|
|
||
|
|
"divs",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,36,CPU_ALL,
|
||
|
|
"divs",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,36,CPU_ALL,
|
||
|
|
"divsu",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,37,CPU_ALL,
|
||
|
|
"divsu",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,37,CPU_ALL,
|
||
|
|
"divus",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,38,CPU_ALL,
|
||
|
|
"divus",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,38,CPU_ALL,
|
||
|
|
"divu",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,39,CPU_ALL,
|
||
|
|
"divu",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,39,CPU_ALL,
|
||
|
|
|
||
|
|
"adds",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,40,CPU_ALL,
|
||
|
|
"adds",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,40,CPU_ALL,
|
||
|
|
"subs",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,41,CPU_ALL,
|
||
|
|
"subs",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,41,CPU_ALL,
|
||
|
|
"shls",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,42,CPU_ALL,
|
||
|
|
"shls",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,42,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"lsls",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,42,CPU_ALL,
|
||
|
|
"lsls",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,42,CPU_ALL,
|
||
|
|
|
||
|
|
"clamp16",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,43,CPU_ALL,
|
||
|
|
"clamp16",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,43,CPU_ALL,
|
||
|
|
|
||
|
|
// All of the following have alternate names, as well as 2- and 3-arg forms
|
||
|
|
"adds32",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,44,CPU_ALL,
|
||
|
|
"adds32",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,44,CPU_ALL,
|
||
|
|
"adds32",OP_REG,OP_REG,0,0,EN_ARITHR32,44,CPU_ALL,
|
||
|
|
"adds32",OP_REG,OP_IMM5,0,0,EN_ARITHI32,44,CPU_ALL,
|
||
|
|
"addscale32",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,44,CPU_ALL,
|
||
|
|
"addscale32",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,44,CPU_ALL,
|
||
|
|
"addscale32",OP_REG,OP_REG,0,0,EN_ARITHR32,44,CPU_ALL,
|
||
|
|
"addscale32",OP_REG,OP_IMM5,0,0,EN_ARITHI32,44,CPU_ALL,
|
||
|
|
"adds64",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,45,CPU_ALL,
|
||
|
|
"adds64",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,45,CPU_ALL,
|
||
|
|
"adds64",OP_REG,OP_REG,0,0,EN_ARITHR32,45,CPU_ALL,
|
||
|
|
"adds64",OP_REG,OP_IMM5,0,0,EN_ARITHI32,45,CPU_ALL,
|
||
|
|
"addscale64",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,45,CPU_ALL,
|
||
|
|
"addscale64",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,45,CPU_ALL,
|
||
|
|
"addscale64",OP_REG,OP_REG,0,0,EN_ARITHR32,45,CPU_ALL,
|
||
|
|
"addscale64",OP_REG,OP_IMM5,0,0,EN_ARITHI32,45,CPU_ALL,
|
||
|
|
"adds128",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,46,CPU_ALL,
|
||
|
|
"adds128",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,46,CPU_ALL,
|
||
|
|
"adds128",OP_REG,OP_REG,0,0,EN_ARITHR32,46,CPU_ALL,
|
||
|
|
"adds128",OP_REG,OP_IMM5,0,0,EN_ARITHI32,46,CPU_ALL,
|
||
|
|
"addscale128",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,46,CPU_ALL,
|
||
|
|
"addscale128",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,46,CPU_ALL,
|
||
|
|
"addscale128",OP_REG,OP_REG,0,0,EN_ARITHR32,46,CPU_ALL,
|
||
|
|
"addscale128",OP_REG,OP_IMM5,0,0,EN_ARITHI32,46,CPU_ALL,
|
||
|
|
"adds256",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,47,CPU_ALL,
|
||
|
|
"adds256",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,47,CPU_ALL,
|
||
|
|
"adds256",OP_REG,OP_REG,0,0,EN_ARITHR32,47,CPU_ALL,
|
||
|
|
"adds256",OP_REG,OP_IMM5,0,0,EN_ARITHI32,47,CPU_ALL,
|
||
|
|
"addscale256",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,47,CPU_ALL,
|
||
|
|
"addscale256",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,47,CPU_ALL,
|
||
|
|
"addscale256",OP_REG,OP_REG,0,0,EN_ARITHR32,47,CPU_ALL,
|
||
|
|
"addscale256",OP_REG,OP_IMM5,0,0,EN_ARITHI32,47,CPU_ALL,
|
||
|
|
|
||
|
|
"count",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,48,CPU_ALL,
|
||
|
|
"count",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,48,CPU_ALL,
|
||
|
|
"count",OP_REG,OP_REG,0,0,EN_ARITHR32,48,CPU_ALL,
|
||
|
|
"count",OP_REG,OP_IMM5,0,0,EN_ARITHI32,48,CPU_ALL,
|
||
|
|
"popcnt",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,48,CPU_ALL,
|
||
|
|
"popcnt",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,48,CPU_ALL,
|
||
|
|
"popcnt",OP_REG,OP_REG,0,0,EN_ARITHR32,48,CPU_ALL,
|
||
|
|
"popcnt",OP_REG,OP_IMM5,0,0,EN_ARITHI32,48,CPU_ALL,
|
||
|
|
|
||
|
|
"subs2",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,49,CPU_ALL,
|
||
|
|
"subs2",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,49,CPU_ALL,
|
||
|
|
"subs2",OP_REG,OP_REG,0,0,EN_ARITHR32,49,CPU_ALL,
|
||
|
|
"subs2",OP_REG,OP_IMM5,0,0,EN_ARITHI32,49,CPU_ALL,
|
||
|
|
"subscale2",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,49,CPU_ALL,
|
||
|
|
"subscale2",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,49,CPU_ALL,
|
||
|
|
"subscale2",OP_REG,OP_REG,0,0,EN_ARITHR32,49,CPU_ALL,
|
||
|
|
"subscale2",OP_REG,OP_IMM5,0,0,EN_ARITHI32,49,CPU_ALL,
|
||
|
|
"subs4",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,50,CPU_ALL,
|
||
|
|
"subs4",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,50,CPU_ALL,
|
||
|
|
"subs4",OP_REG,OP_REG,0,0,EN_ARITHR32,50,CPU_ALL,
|
||
|
|
"subs4",OP_REG,OP_IMM5,0,0,EN_ARITHI32,50,CPU_ALL,
|
||
|
|
"subscale4",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,50,CPU_ALL,
|
||
|
|
"subscale4",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,50,CPU_ALL,
|
||
|
|
"subscale4",OP_REG,OP_REG,0,0,EN_ARITHR32,50,CPU_ALL,
|
||
|
|
"subscale4",OP_REG,OP_IMM5,0,0,EN_ARITHI32,50,CPU_ALL,
|
||
|
|
"subs8",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,51,CPU_ALL,
|
||
|
|
"subs8",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,51,CPU_ALL,
|
||
|
|
"subs8",OP_REG,OP_REG,0,0,EN_ARITHR32,51,CPU_ALL,
|
||
|
|
"subs8",OP_REG,OP_IMM5,0,0,EN_ARITHI32,51,CPU_ALL,
|
||
|
|
"subscale8",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,51,CPU_ALL,
|
||
|
|
"subscale8",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,51,CPU_ALL,
|
||
|
|
"subscale8",OP_REG,OP_REG,0,0,EN_ARITHR32,51,CPU_ALL,
|
||
|
|
"subscale8",OP_REG,OP_IMM5,0,0,EN_ARITHI32,51,CPU_ALL,
|
||
|
|
"subs16",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,52,CPU_ALL,
|
||
|
|
"subs16",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,52,CPU_ALL,
|
||
|
|
"subs16",OP_REG,OP_REG,0,0,EN_ARITHR32,52,CPU_ALL,
|
||
|
|
"subs16",OP_REG,OP_IMM5,0,0,EN_ARITHI32,52,CPU_ALL,
|
||
|
|
"subscale16",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,52,CPU_ALL,
|
||
|
|
"subscale16",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,52,CPU_ALL,
|
||
|
|
"subscale16",OP_REG,OP_REG,0,0,EN_ARITHR32,52,CPU_ALL,
|
||
|
|
"subscale16",OP_REG,OP_IMM5,0,0,EN_ARITHI32,52,CPU_ALL,
|
||
|
|
"subs32",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,53,CPU_ALL,
|
||
|
|
"subs32",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,53,CPU_ALL,
|
||
|
|
"subs32",OP_REG,OP_REG,0,0,EN_ARITHR32,53,CPU_ALL,
|
||
|
|
"subs32",OP_REG,OP_IMM5,0,0,EN_ARITHI32,53,CPU_ALL,
|
||
|
|
"subscale32",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,53,CPU_ALL,
|
||
|
|
"subscale32",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,53,CPU_ALL,
|
||
|
|
"subscale32",OP_REG,OP_REG,0,0,EN_ARITHR32,53,CPU_ALL,
|
||
|
|
"subscale32",OP_REG,OP_IMM5,0,0,EN_ARITHI32,53,CPU_ALL,
|
||
|
|
"subs64",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,54,CPU_ALL,
|
||
|
|
"subs64",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,54,CPU_ALL,
|
||
|
|
"subs64",OP_REG,OP_REG,0,0,EN_ARITHR32,54,CPU_ALL,
|
||
|
|
"subs64",OP_REG,OP_IMM5,0,0,EN_ARITHI32,54,CPU_ALL,
|
||
|
|
"subscale64",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,54,CPU_ALL,
|
||
|
|
"subscale64",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,54,CPU_ALL,
|
||
|
|
"subscale64",OP_REG,OP_REG,0,0,EN_ARITHR32,54,CPU_ALL,
|
||
|
|
"subscale64",OP_REG,OP_IMM5,0,0,EN_ARITHI32,54,CPU_ALL,
|
||
|
|
"subs128",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,55,CPU_ALL,
|
||
|
|
"subs128",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,55,CPU_ALL,
|
||
|
|
"subs128",OP_REG,OP_REG,0,0,EN_ARITHR32,55,CPU_ALL,
|
||
|
|
"subs128",OP_REG,OP_IMM5,0,0,EN_ARITHI32,55,CPU_ALL,
|
||
|
|
"subscale128",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,55,CPU_ALL,
|
||
|
|
"subscale128",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,55,CPU_ALL,
|
||
|
|
"subscale128",OP_REG,OP_REG,0,0,EN_ARITHR32,55,CPU_ALL,
|
||
|
|
"subscale128",OP_REG,OP_IMM5,0,0,EN_ARITHI32,55,CPU_ALL,
|
||
|
|
"subs256",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,56,CPU_ALL,
|
||
|
|
"subs256",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,56,CPU_ALL,
|
||
|
|
"subs256",OP_REG,OP_REG,0,0,EN_ARITHR32,56,CPU_ALL,
|
||
|
|
"subs256",OP_REG,OP_IMM5,0,0,EN_ARITHI32,56,CPU_ALL,
|
||
|
|
"subscale256",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,56,CPU_ALL,
|
||
|
|
"subscale256",OP_REG,OP_REG,OP_IMM5,0,EN_ARITHI32,56,CPU_ALL,
|
||
|
|
"subscale256",OP_REG,OP_REG,0,0,EN_ARITHR32,56,CPU_ALL,
|
||
|
|
"subscale256",OP_REG,OP_IMM5,0,0,EN_ARITHI32,56,CPU_ALL,
|
||
|
|
|
||
|
|
|
||
|
|
"bkpt",0,0,0,0,EN_FIX16,0x00000000,CPU_ALL,
|
||
|
|
"nop",0,0,0,0,EN_FIX16,0x00010000,CPU_ALL,
|
||
|
|
"sleep",0,0,0,0,EN_FIX16,0x00020000,CPU_ALL,
|
||
|
|
"user",0,0,0,0,EN_FIX16,0x00030000,CPU_ALL,
|
||
|
|
"ei",0,0,0,0,EN_FIX16,0x00040000,CPU_ALL,
|
||
|
|
"di",0,0,0,0,EN_FIX16,0x00050000,CPU_ALL,
|
||
|
|
"cbclr",0,0,0,0,EN_FIX16,0x00060000,CPU_ALL,
|
||
|
|
"cbinc",0,0,0,0,EN_FIX16,0x00070000,CPU_ALL,
|
||
|
|
"cbchg",0,0,0,0,EN_FIX16,0x00080000,CPU_ALL,
|
||
|
|
"cbdec",0,0,0,0,EN_FIX16,0x00090000,CPU_ALL,
|
||
|
|
"rts",0,0,0,0,EN_FIX16,0x005A0000,CPU_ALL,
|
||
|
|
"rti",0,0,0,0,EN_FIX16,0x000A0000,CPU_ALL,
|
||
|
|
|
||
|
|
"b",OP_REG,0,0,0,EN_IBRANCH16,0x00400000,CPU_ALL,
|
||
|
|
"b",OP_REL,0,0,0,EN_RBRANCH16,0,CPU_ALL,
|
||
|
|
"b",OP_REL,0,0,0,EN_RBRANCH32,0x90000000,CPU_ALL,
|
||
|
|
|
||
|
|
|
||
|
|
"bl",OP_REG,0,0,0,EN_IBRANCH16,0x00600000,CPU_ALL,
|
||
|
|
"bl",OP_REL,0,0,0,EN_RBRANCH32,0x90800000,CPU_ALL,
|
||
|
|
|
||
|
|
|
||
|
|
"tbb",OP_REG,0,0,0,EN_IBRANCH16,0x00800000,CPU_ALL,
|
||
|
|
"tbs",OP_REG,0,0,0,EN_IBRANCH16,0x00A00000,CPU_ALL,
|
||
|
|
|
||
|
|
"pop",OP_PC,0,0,0,EN_FIX16,0x036f0000,CPU_ALL,
|
||
|
|
"pop",OP_MREG,0,0,0,EN_MREG16,0x02000000,CPU_ALL,
|
||
|
|
"pop",OP_MREG,OP_PC,0,0,EN_MREG16,0x03000000,CPU_ALL,
|
||
|
|
|
||
|
|
"push",OP_LR,0,0,0,EN_FIX16,0x03ef0000,CPU_ALL,
|
||
|
|
"push",OP_MREG,0,0,0,EN_MREG16,0x02800000,CPU_ALL,
|
||
|
|
"push",OP_MREG,OP_LR,0,0,EN_MREG16,0x03800000,CPU_ALL,
|
||
|
|
|
||
|
|
"ldb",OP_REG,OP_POSTINC,0,0,EN_MEMPOSTINC,4,CPU_ALL,
|
||
|
|
"ldb",OP_REG,OP_PREDEC,0,0,EN_MEMPREDEC,4,CPU_ALL,
|
||
|
|
"ldb",OP_REG,OP_REGIND,0,0,EN_MEMREG32,4,CPU_ALL,
|
||
|
|
"ldb",OP_SREG,OP_IND,0,0,EN_MEMREG16,4,CPU_ALL,
|
||
|
|
"ldb",OP_REG,OP_IMMINDSD,0,0,EN_MEM16DISP32,0xA8800000,CPU_ALL,
|
||
|
|
"ldb",OP_REG,OP_IMMINDSP,0,0,EN_MEM16DISP32,0xA9800000,CPU_ALL,
|
||
|
|
"ldb",OP_REG,OP_IMMINDPC,0,0,EN_MEM16DISP32,0xAA800000,CPU_ALL,
|
||
|
|
"ldb",OP_REG,OP_IMMINDR0,0,0,EN_MEM16DISP32,0xAB800000,CPU_ALL,
|
||
|
|
"ldb",OP_REG,OP_IMMIND,0,0,EN_MEM12DISP32,4,CPU_ALL,
|
||
|
|
"ldb",OP_REG,OP_IMMIND,0,0,EN_MEMDISP32,4,CPU_ALL,
|
||
|
|
"ldb",OP_REG,OP_IMMIND,0,0,EN_MEM48,4,CPU_ALL,
|
||
|
|
|
||
|
|
"ldh",OP_REG,OP_POSTINC,0,0,EN_MEMPOSTINC,2,CPU_ALL,
|
||
|
|
"ldh",OP_REG,OP_PREDEC,0,0,EN_MEMPREDEC,2,CPU_ALL,
|
||
|
|
"ldh",OP_REG,OP_REGIND,0,0,EN_MEMREG32,2,CPU_ALL,
|
||
|
|
"ldh",OP_SREG,OP_IND,0,0,EN_MEMREG16,2,CPU_ALL,
|
||
|
|
"ldh",OP_REG,OP_IMMINDSD,0,0,EN_MEM16DISP32,0xA8400000,CPU_ALL,
|
||
|
|
"ldh",OP_REG,OP_IMMINDSP,0,0,EN_MEM16DISP32,0xA9400000,CPU_ALL,
|
||
|
|
"ldh",OP_REG,OP_IMMINDPC,0,0,EN_MEM16DISP32,0xAA400000,CPU_ALL,
|
||
|
|
"ldh",OP_REG,OP_IMMINDR0,0,0,EN_MEM16DISP32,0xAB400000,CPU_ALL,
|
||
|
|
"ldh",OP_REG,OP_IMMIND,0,0,EN_MEM12DISP32,2,CPU_ALL,
|
||
|
|
"ldh",OP_REG,OP_IMMIND,0,0,EN_MEMDISP32,2,CPU_ALL,
|
||
|
|
"ldh",OP_REG,OP_IMMIND,0,0,EN_MEM48,2,CPU_ALL,
|
||
|
|
|
||
|
|
|
||
|
|
"ldhs",OP_REG,OP_POSTINC,0,0,EN_MEMPOSTINC,6,CPU_ALL,
|
||
|
|
"ldhs",OP_REG,OP_PREDEC,0,0,EN_MEMPREDEC,6,CPU_ALL,
|
||
|
|
"ldhs",OP_REG,OP_REGIND,0,0,EN_MEMREG32,6,CPU_ALL,
|
||
|
|
"ldhs",OP_SREG,OP_IND,0,0,EN_MEMREG16,6,CPU_ALL,
|
||
|
|
"ldhs",OP_REG,OP_IMMINDSD,0,0,EN_MEM16DISP32,0xA8C00000,CPU_ALL,
|
||
|
|
"ldhs",OP_REG,OP_IMMINDSP,0,0,EN_MEM16DISP32,0xA9C00000,CPU_ALL,
|
||
|
|
"ldhs",OP_REG,OP_IMMINDPC,0,0,EN_MEM16DISP32,0xAAC00000,CPU_ALL,
|
||
|
|
"ldhs",OP_REG,OP_IMMINDR0,0,0,EN_MEM16DISP32,0xABC00000,CPU_ALL,
|
||
|
|
"ldhs",OP_REG,OP_IMMIND,0,0,EN_MEM12DISP32,6,CPU_ALL,
|
||
|
|
"ldhs",OP_REG,OP_IMMIND,0,0,EN_MEMDISP32,6,CPU_ALL,
|
||
|
|
"ldhs",OP_REG,OP_IMMIND,0,0,EN_MEM48,6,CPU_ALL,
|
||
|
|
|
||
|
|
|
||
|
|
"ld",OP_REG,OP_POSTINC,0,0,EN_MEMPOSTINC,0,CPU_ALL,
|
||
|
|
"ld",OP_REG,OP_PREDEC,0,0,EN_MEMPREDEC,0,CPU_ALL,
|
||
|
|
"ld",OP_REG,OP_REGIND,0,0,EN_MEMREG32,0,CPU_ALL,
|
||
|
|
"ld",OP_SREG,OP_IND,0,0,EN_MEMREG16,0,CPU_ALL,
|
||
|
|
"ld",OP_REG,OP_IMMINDSD,0,0,EN_MEM16DISP32,0xA8000000,CPU_ALL,
|
||
|
|
"ld",OP_REG,OP_IMMINDSP,0,0,EN_MEM16DISP32,0xA9000000,CPU_ALL,
|
||
|
|
"ld",OP_REG,OP_IMMINDPC,0,0,EN_MEM16DISP32,0xAA000000,CPU_ALL,
|
||
|
|
"ld",OP_REG,OP_IMMINDR0,0,0,EN_MEM16DISP32,0xAB000000,CPU_ALL,
|
||
|
|
"ld",OP_SREG,OP_IMMINDSP,0,0,EN_MEMSTACK16,0,CPU_ALL,
|
||
|
|
"ld",OP_SREG,OP_IMMINDS,0,0,EN_MEMDISP16,0,CPU_ALL,
|
||
|
|
"ld",OP_REG,OP_IMMIND,0,0,EN_MEM12DISP32,0,CPU_ALL,
|
||
|
|
"ld",OP_REG,OP_IMMIND,0,0,EN_MEMDISP32,0,CPU_ALL,
|
||
|
|
"ld",OP_REG,OP_IMMIND,0,0,EN_MEM48,0,CPU_ALL,
|
||
|
|
|
||
|
|
"stb",OP_REG,OP_POSTINC,0,0,EN_MEMPOSTINC,5,CPU_ALL,
|
||
|
|
"stb",OP_REG,OP_PREDEC,0,0,EN_MEMPREDEC,5,CPU_ALL,
|
||
|
|
"stb",OP_REG,OP_REGIND,0,0,EN_MEMREG32,5,CPU_ALL,
|
||
|
|
"stb",OP_SREG,OP_IND,0,0,EN_MEMREG16,5,CPU_ALL,
|
||
|
|
"stb",OP_REG,OP_IMMINDSD,0,0,EN_MEM16DISP32,0xA8A00000,CPU_ALL,
|
||
|
|
"stb",OP_REG,OP_IMMINDSP,0,0,EN_MEM16DISP32,0xA9A00000,CPU_ALL,
|
||
|
|
"stb",OP_REG,OP_IMMINDPC,0,0,EN_MEM16DISP32,0xAAA00000,CPU_ALL,
|
||
|
|
"stb",OP_REG,OP_IMMINDR0,0,0,EN_MEM16DISP32,0xABA00000,CPU_ALL,
|
||
|
|
"stb",OP_REG,OP_IMMIND,0,0,EN_MEM12DISP32,5,CPU_ALL,
|
||
|
|
"stb",OP_REG,OP_IMMIND,0,0,EN_MEMDISP32,5,CPU_ALL,
|
||
|
|
"stb",OP_REG,OP_IMMIND,0,0,EN_MEM48,5,CPU_ALL,
|
||
|
|
|
||
|
|
"sth",OP_REG,OP_POSTINC,0,0,EN_MEMPOSTINC,3,CPU_ALL,
|
||
|
|
"sth",OP_REG,OP_PREDEC,0,0,EN_MEMPREDEC,3,CPU_ALL,
|
||
|
|
"sth",OP_REG,OP_REGIND,0,0,EN_MEMREG32,3,CPU_ALL,
|
||
|
|
"sth",OP_SREG,OP_IND,0,0,EN_MEMREG16,3,CPU_ALL,
|
||
|
|
"sth",OP_REG,OP_IMMINDSD,0,0,EN_MEM16DISP32,0xA8600000,CPU_ALL,
|
||
|
|
"sth",OP_REG,OP_IMMINDSP,0,0,EN_MEM16DISP32,0xA9600000,CPU_ALL,
|
||
|
|
"sth",OP_REG,OP_IMMINDPC,0,0,EN_MEM16DISP32,0xAA600000,CPU_ALL,
|
||
|
|
"sth",OP_REG,OP_IMMINDR0,0,0,EN_MEM16DISP32,0xAB600000,CPU_ALL,
|
||
|
|
"sth",OP_REG,OP_IMMIND,0,0,EN_MEM12DISP32,3,CPU_ALL,
|
||
|
|
"sth",OP_REG,OP_IMMIND,0,0,EN_MEMDISP32,3,CPU_ALL,
|
||
|
|
"sth",OP_REG,OP_IMMIND,0,0,EN_MEM48,3,CPU_ALL,
|
||
|
|
|
||
|
|
"st",OP_REG,OP_POSTINC,0,0,EN_MEMPOSTINC,1,CPU_ALL,
|
||
|
|
"st",OP_REG,OP_PREDEC,0,0,EN_MEMPREDEC,1,CPU_ALL,
|
||
|
|
"st",OP_REG,OP_REGIND,0,0,EN_MEMREG32,1,CPU_ALL,
|
||
|
|
"st",OP_SREG,OP_IND,0,0,EN_MEMREG16,1,CPU_ALL,
|
||
|
|
"st",OP_REG,OP_IMMINDSD,0,0,EN_MEM16DISP32,0xA8200000,CPU_ALL,
|
||
|
|
"st",OP_REG,OP_IMMINDSP,0,0,EN_MEM16DISP32,0xA9200000,CPU_ALL,
|
||
|
|
"st",OP_REG,OP_IMMINDPC,0,0,EN_MEM16DISP32,0xAA200000,CPU_ALL,
|
||
|
|
"st",OP_REG,OP_IMMINDR0,0,0,EN_MEM16DISP32,0xAB200000,CPU_ALL,
|
||
|
|
"st",OP_SREG,OP_IMMINDSP,0,0,EN_MEMSTACK16,1,CPU_ALL,
|
||
|
|
"st",OP_SREG,OP_IMMINDS,0,0,EN_MEMDISP16,1,CPU_ALL,
|
||
|
|
"st",OP_REG,OP_IMMIND,0,0,EN_MEM12DISP32,1,CPU_ALL,
|
||
|
|
"st",OP_REG,OP_IMMIND,0,0,EN_MEMDISP32,1,CPU_ALL,
|
||
|
|
"st",OP_REG,OP_IMMIND,0,0,EN_MEM48,1,CPU_ALL,
|
||
|
|
|
||
|
|
"lea",OP_REG,OP_IMMINDSP,0,0,EN_LEA16,0,CPU_ALL,
|
||
|
|
"lea",OP_REG,OP_IMMINDPC,0,0,EN_LEA48,0,CPU_ALL,
|
||
|
|
|
||
|
|
"addcmpb",OP_SREG,OP_SREG,OP_SREG,OP_REL,EN_ADDCMPB32,0,CPU_ALL,
|
||
|
|
"addcmpb",OP_SREG,OP_IMM4,OP_SREG,OP_REL,EN_ADDCMPB32,1,CPU_ALL,
|
||
|
|
"addcmpb",OP_SREG,OP_SREG,OP_IMM6,OP_REL,EN_ADDCMPB32,2,CPU_ALL,
|
||
|
|
"addcmpb",OP_SREG,OP_IMM4,OP_IMM6,OP_REL,EN_ADDCMPB32,3,CPU_ALL,
|
||
|
|
/*dummy for large offsets */
|
||
|
|
"addcmpb",OP_SREG,OP_SREG,OP_SREG,OP_REL,EN_ADDCMPB64,0,CPU_ALL,
|
||
|
|
"addcmpb",OP_SREG,OP_IMM4,OP_SREG,OP_REL,EN_ADDCMPB64,1,CPU_ALL,
|
||
|
|
"addcmpb",OP_SREG,OP_SREG,OP_IMM6,OP_REL,EN_ADDCMPB64,2,CPU_ALL,
|
||
|
|
"addcmpb",OP_SREG,OP_IMM4,OP_IMM6,OP_REL,EN_ADDCMPB64,3,CPU_ALL,
|
||
|
|
|
||
|
|
"fadd",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|0,CPU_ALL,
|
||
|
|
"fsub",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|1,CPU_ALL,
|
||
|
|
"fmul",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|2,CPU_ALL,
|
||
|
|
"fdiv",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|3,CPU_ALL,
|
||
|
|
"fcmp",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|4,CPU_ALL,
|
||
|
|
"fabs",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|5,CPU_ALL,
|
||
|
|
"frsb",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|6,CPU_ALL,
|
||
|
|
"fmax",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|7,CPU_ALL,
|
||
|
|
"frcp",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|8,CPU_ALL,
|
||
|
|
"frsqrt",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|9,CPU_ALL,
|
||
|
|
"fnmul",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|10,CPU_ALL,
|
||
|
|
"fmin",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|11,CPU_ALL,
|
||
|
|
|
||
|
|
"fld1",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|12,CPU_ALL,
|
||
|
|
"fld0",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|13,CPU_ALL,
|
||
|
|
// Alternate names
|
||
|
|
"fceil",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|12,CPU_ALL,
|
||
|
|
"ffloor",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|13,CPU_ALL,
|
||
|
|
|
||
|
|
"log2",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|14,CPU_ALL,
|
||
|
|
"exp2",OP_REG,OP_REG,OP_REG,0,EN_ARITHR32,64|15,CPU_ALL,
|
||
|
|
"ftrunc",OP_REG,OP_REG,0,0,EN_FUNARY32,64|16,CPU_ALL,
|
||
|
|
"floor",OP_REG,OP_REG,0,0,EN_FUNARY32,64|17,CPU_ALL,
|
||
|
|
"flts",OP_REG,OP_REG,0,0,EN_FUNARY32,64|18,CPU_ALL,
|
||
|
|
"fltu",OP_REG,OP_REG,0,0,EN_FUNARY32,64|19,CPU_ALL,
|
||
|
|
|
||
|
|
"vld",OP_VREG,OP_IND,0,0,EN_VLOAD48,2,CPU_ALL,
|
||
|
|
"vld",OP_VREGM,OP_VIND,0,0,EN_VLOAD80,2,CPU_ALL,
|
||
|
|
|
||
|
|
"vldb",OP_VREG,OP_IND,0,0,EN_VLOAD48,0,CPU_ALL,
|
||
|
|
"vldb",OP_VREGM,OP_VIND,0,0,EN_VLOAD80,0,CPU_ALL,
|
||
|
|
|
||
|
|
"vldh",OP_VREG,OP_IND,0,0,EN_VLOAD48,1,CPU_ALL,
|
||
|
|
"vldh",OP_VREGM,OP_VIND,0,0,EN_VLOAD80,1,CPU_ALL,
|
||
|
|
|
||
|
|
"vlookupmh",OP_VREGM,OP_VIND,0,0,EN_VLOAD80,(1<<2)|2,CPU_ALL,
|
||
|
|
"vlookupmhs",OP_VREG,OP_VIND,0,0,EN_VLOAD48,(1<<2)|2,CPU_ALL,
|
||
|
|
|
||
|
|
"vlookupmhb",OP_VREGM,OP_VIND,0,0,EN_VLOAD80,(1<<2)|0,CPU_ALL,
|
||
|
|
"vlookupmhsb",OP_VREG,OP_VIND,0,0,EN_VLOAD48,(1<<2)|0,CPU_ALL,
|
||
|
|
|
||
|
|
"vlookupmhh",OP_VREGM,OP_VIND,0,0,EN_VLOAD80,(1<<2)|1,CPU_ALL,
|
||
|
|
"vlookupmhsh",OP_VREG,OP_VIND,0,0,EN_VLOAD48,(1<<2)|1,CPU_ALL,
|
||
|
|
|
||
|
|
"vlookupml",OP_VREGM,OP_VIND,0,0,EN_VLOAD80,(2<<2)|2,CPU_ALL,
|
||
|
|
"vlookupmls",OP_VREG,OP_VIND,0,0,EN_VLOAD48,(2<<2)|2,CPU_ALL,
|
||
|
|
|
||
|
|
"vlookupmlb",OP_VREGM,OP_VIND,0,0,EN_VLOAD80,(2<<2)|0,CPU_ALL,
|
||
|
|
"vlookupmlsb",OP_VREG,OP_VIND,0,0,EN_VLOAD48,(2<<2)|0,CPU_ALL,
|
||
|
|
|
||
|
|
"vlookupmlh",OP_VREGM,OP_VIND,0,0,EN_VLOAD80,(2<<2)|1,CPU_ALL,
|
||
|
|
"vlookupmlsh",OP_VREG,OP_VIND,0,0,EN_VLOAD48,(2<<2)|1,CPU_ALL,
|
||
|
|
|
||
|
|
"vst",OP_VREG,OP_IND,0,0,EN_VSTORE48,(4<<2)|2,CPU_ALL,
|
||
|
|
"vst",OP_VREGA80,OP_VIND,0,0,EN_VSTORE80,(4<<2)|2,CPU_ALL,
|
||
|
|
|
||
|
|
"vstb",OP_VREG,OP_IND,0,0,EN_VSTORE48,(4<<2)|0,CPU_ALL,
|
||
|
|
"vstb",OP_VREGA80,OP_VIND,0,0,EN_VSTORE80,(4<<2)|0,CPU_ALL,
|
||
|
|
|
||
|
|
"vsth",OP_VREG,OP_IND,0,0,EN_VSTORE48,(4<<2)|1,CPU_ALL,
|
||
|
|
"vsth",OP_VREGA80,OP_VIND,0,0,EN_VSTORE80,(4<<2)|1,CPU_ALL,
|
||
|
|
|
||
|
|
"vindexwritemh",OP_VREGA80,OP_VIND,0,0,EN_VSTORE80,(5<<2)|2,CPU_ALL,
|
||
|
|
"vindexwritemhs",OP_VREG,OP_VIND,0,0,EN_VSTORE48,(5<<2)|2,CPU_ALL,
|
||
|
|
|
||
|
|
"vindexwritemhb",OP_VREGA80,OP_VIND,0,0,EN_VSTORE80,(5<<2)|0,CPU_ALL,
|
||
|
|
"vindexwritemhsb",OP_VREG,OP_VIND,0,0,EN_VSTORE48,(5<<2)|0,CPU_ALL,
|
||
|
|
|
||
|
|
"vindexwritemhh",OP_VREGA80,OP_VIND,0,0,EN_VSTORE80,(5<<2)|1,CPU_ALL,
|
||
|
|
"vindexwritemhsh",OP_VREG,OP_VIND,0,0,EN_VSTORE48,(5<<2)|1,CPU_ALL,
|
||
|
|
|
||
|
|
"vindexwriteml",OP_VREGA80,OP_VIND,0,0,EN_VSTORE80,(6<<2)|2,CPU_ALL,
|
||
|
|
"vindexwritemls",OP_VREG,OP_VIND,0,0,EN_VSTORE48,(6<<2)|2,CPU_ALL,
|
||
|
|
|
||
|
|
"vindexwritemlb",OP_VREGA80,OP_VIND,0,0,EN_VSTORE80,(6<<2)|0,CPU_ALL,
|
||
|
|
"vindexwritemlsb",OP_VREG,OP_VIND,0,0,EN_VSTORE48,(6<<2)|0,CPU_ALL,
|
||
|
|
|
||
|
|
"vindexwritemlh",OP_VREGA80,OP_VIND,0,0,EN_VSTORE80,(6<<2)|1,CPU_ALL,
|
||
|
|
"vindexwritemlsh",OP_VREG,OP_VIND,0,0,EN_VSTORE48,(6<<2)|1,CPU_ALL,
|
||
|
|
|
||
|
|
"vreadlut",OP_VREG,OP_VREG,0,0,EN_VREAD48,(8<<2)|2,CPU_ALL,
|
||
|
|
"vreadlut",OP_VREGM,OP_VREGMM,0,0,EN_VREAD80,(8<<2)|2,CPU_ALL,
|
||
|
|
"vreadlut",OP_VREG,OP_IMM6,0,0,EN_VREADI48,(8<<2)|2,CPU_ALL,
|
||
|
|
"vreadlut",OP_VREGM,OP_IMM32M,0,0,EN_VREADI80,(8<<2)|2,CPU_ALL,
|
||
|
|
|
||
|
|
"vreadlutb",OP_VREG,OP_VREG,0,0,EN_VREAD48,(8<<2)|0,CPU_ALL,
|
||
|
|
"vreadlutb",OP_VREGM,OP_VREGMM,0,0,EN_VREAD80,(8<<2)|0,CPU_ALL,
|
||
|
|
"vreadlutb",OP_VREG,OP_IMM6,0,0,EN_VREADI48,(8<<2)|0,CPU_ALL,
|
||
|
|
"vreadlutb",OP_VREGM,OP_IMM32M,0,0,EN_VREADI80,(8<<2)|0,CPU_ALL,
|
||
|
|
|
||
|
|
"vreadluth",OP_VREG,OP_VREG,0,0,EN_VREAD48,(8<<2)|1,CPU_ALL,
|
||
|
|
"vreadluth",OP_VREGM,OP_VREGMM,0,0,EN_VREAD80,(8<<2)|1,CPU_ALL,
|
||
|
|
"vreadluth",OP_VREG,OP_IMM6,0,0,EN_VREADI48,(8<<2)|1,CPU_ALL,
|
||
|
|
"vreadluth",OP_VREGM,OP_IMM32M,0,0,EN_VREADI80,(8<<2)|1,CPU_ALL,
|
||
|
|
|
||
|
|
"vwritelut",OP_VREG,OP_VREG,0,0,EN_VWRITE48,(9<<2)|2,CPU_ALL,
|
||
|
|
"vwritelut",OP_VREGM,OP_VREGMM,0,0,EN_VWRITE80,(9<<2)|2,CPU_ALL,
|
||
|
|
"vwritelut",OP_VREG,OP_IMM6,0,0,EN_VWRITEI48,(9<<2)|2,CPU_ALL,
|
||
|
|
"vwritelut",OP_VREGM,OP_IMM32M,0,0,EN_VWRITEI80,(9<<2)|2,CPU_ALL,
|
||
|
|
|
||
|
|
"vwritelutb",OP_VREG,OP_VREG,0,0,EN_VWRITE48,(9<<2)|0,CPU_ALL,
|
||
|
|
"vwritelutb",OP_VREGM,OP_VREGMM,0,0,EN_VWRITE80,(9<<2)|0,CPU_ALL,
|
||
|
|
"vwritelutb",OP_VREG,OP_IMM6,0,0,EN_VWRITEI48,(9<<2)|0,CPU_ALL,
|
||
|
|
"vwritelutb",OP_VREGM,OP_IMM32M,0,0,EN_VWRITEI80,(9<<2)|0,CPU_ALL,
|
||
|
|
|
||
|
|
"vwriteluth",OP_VREG,OP_VREG,0,0,EN_VWRITE48,(9<<2)|1,CPU_ALL,
|
||
|
|
"vwriteluth",OP_VREGM,OP_VREGMM,0,0,EN_VWRITE80,(9<<2)|1,CPU_ALL,
|
||
|
|
"vwriteluth",OP_VREG,OP_IMM6,0,0,EN_VWRITEI48,(9<<2)|1,CPU_ALL,
|
||
|
|
"vwriteluth",OP_VREGM,OP_IMM32M,0,0,EN_VWRITEI80,(9<<2)|1,CPU_ALL,
|
||
|
|
|
||
|
|
"vreadacc",OP_VREG,OP_VREG,0,0,EN_VREAD48,(24<<2)|0,CPU_ALL,
|
||
|
|
"vreadacc",OP_VREGM,OP_VREGMM,0,0,EN_VREAD80,(24<<2)|0,CPU_ALL,
|
||
|
|
"vreadacc",OP_VREG,OP_IMM6,0,0,EN_VREADI48,(24<<2)|0,CPU_ALL,
|
||
|
|
"vreadacc",OP_VREGM,OP_IMM32M,0,0,EN_VREADI80,(24<<2)|0,CPU_ALL,
|
||
|
|
|
||
|
|
"vreadaccs32",OP_VREG,OP_VREG,0,0,EN_VREAD48,(24<<2)|1,CPU_ALL,
|
||
|
|
"vreadaccs32",OP_VREGM,OP_VREGMM,0,0,EN_VREAD80,(24<<2)|1,CPU_ALL,
|
||
|
|
"vreadaccs32",OP_VREG,OP_IMM6,0,0,EN_VREADI48,(24<<2)|1,CPU_ALL,
|
||
|
|
"vreadaccs32",OP_VREGM,OP_IMM32M,0,0,EN_VREADI80,(24<<2)|1,CPU_ALL,
|
||
|
|
|
||
|
|
"vreadaccs16",OP_VREG,OP_VREG,0,0,EN_VREAD48,(24<<2)|3,CPU_ALL,
|
||
|
|
"vreadaccs16",OP_VREGM,OP_VREGMM,0,0,EN_VREAD80,(24<<2)|3,CPU_ALL,
|
||
|
|
"vreadaccs16",OP_VREG,OP_IMM6,0,0,EN_VREADI48,(24<<2)|3,CPU_ALL,
|
||
|
|
"vreadaccs16",OP_VREGM,OP_IMM32M,0,0,EN_VREADI80,(24<<2)|3,CPU_ALL,
|
||
|
|
|
||
|
|
"vmov",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,0,CPU_ALL,
|
||
|
|
"vmov",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,0,CPU_ALL,
|
||
|
|
"vmov",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,0,CPU_ALL,
|
||
|
|
"vmov",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,0,CPU_ALL,
|
||
|
|
"vmov",OP_VREG,OP_VREG,0,0,EN_VARITHR48,0,CPU_ALL,
|
||
|
|
"vmov",OP_VREGM,OP_VREGMM,0,0,EN_VARITHR80,0,CPU_ALL,
|
||
|
|
"vmov",OP_VREG,OP_IMM6,0,0,EN_VARITHI48,0,CPU_ALL,
|
||
|
|
"vmov",OP_VREGM,OP_IMM32M,0,0,EN_VARITHI80,0,CPU_ALL,
|
||
|
|
|
||
|
|
"vmask",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,1,CPU_ALL,
|
||
|
|
"vmask",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,1,CPU_ALL,
|
||
|
|
"vmask",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,1,CPU_ALL,
|
||
|
|
"vmask",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,1,CPU_ALL,
|
||
|
|
|
||
|
|
"vcmbod",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,2,CPU_ALL,
|
||
|
|
"vcmbod",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,2,CPU_ALL,
|
||
|
|
"vcmbod",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,2,CPU_ALL,
|
||
|
|
"vcmbod",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,2,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vodd",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,2,CPU_ALL,
|
||
|
|
"vodd",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,2,CPU_ALL,
|
||
|
|
"vodd",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,2,CPU_ALL,
|
||
|
|
"vodd",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,2,CPU_ALL,
|
||
|
|
|
||
|
|
"vcmbev",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,3,CPU_ALL,
|
||
|
|
"vcmbev",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,3,CPU_ALL,
|
||
|
|
"vcmbev",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,3,CPU_ALL,
|
||
|
|
"vcmbev",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,3,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"veven",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,3,CPU_ALL,
|
||
|
|
"veven",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,3,CPU_ALL,
|
||
|
|
"veven",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,3,CPU_ALL,
|
||
|
|
"veven",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,3,CPU_ALL,
|
||
|
|
|
||
|
|
"valtl",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,4,CPU_ALL,
|
||
|
|
"valtl",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,4,CPU_ALL,
|
||
|
|
"valtl",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,4,CPU_ALL,
|
||
|
|
"valtl",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,4,CPU_ALL,
|
||
|
|
|
||
|
|
"valtu",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,5,CPU_ALL,
|
||
|
|
"valtu",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,5,CPU_ALL,
|
||
|
|
"valtu",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,5,CPU_ALL,
|
||
|
|
"valtu",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,5,CPU_ALL,
|
||
|
|
|
||
|
|
"vbrev",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,6,CPU_ALL,
|
||
|
|
"vbrev",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,6,CPU_ALL,
|
||
|
|
"vbrev",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,6,CPU_ALL,
|
||
|
|
"vbrev",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,6,CPU_ALL,
|
||
|
|
|
||
|
|
"vror",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,7,CPU_ALL,
|
||
|
|
"vror",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,7,CPU_ALL,
|
||
|
|
"vror",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,7,CPU_ALL,
|
||
|
|
"vror",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,7,CPU_ALL,
|
||
|
|
|
||
|
|
"vlsl",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,8,CPU_ALL,
|
||
|
|
"vlsl",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,8,CPU_ALL,
|
||
|
|
"vlsl",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,8,CPU_ALL,
|
||
|
|
"vlsl",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,8,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vshl",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,8,CPU_ALL,
|
||
|
|
"vshl",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,8,CPU_ALL,
|
||
|
|
"vshl",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,8,CPU_ALL,
|
||
|
|
"vshl",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,8,CPU_ALL,
|
||
|
|
|
||
|
|
"vasl",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,9,CPU_ALL,
|
||
|
|
"vasl",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,9,CPU_ALL,
|
||
|
|
"vasl",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,9,CPU_ALL,
|
||
|
|
"vasl",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,9,CPU_ALL,
|
||
|
|
|
||
|
|
"vlsr",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,10,CPU_ALL,
|
||
|
|
"vlsr",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,10,CPU_ALL,
|
||
|
|
"vlsr",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,10,CPU_ALL,
|
||
|
|
"vlsr",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,10,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vshr",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,10,CPU_ALL,
|
||
|
|
"vshr",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,10,CPU_ALL,
|
||
|
|
"vshr",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,10,CPU_ALL,
|
||
|
|
"vshr",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,10,CPU_ALL,
|
||
|
|
|
||
|
|
"vasr",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,11,CPU_ALL,
|
||
|
|
"vasr",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,11,CPU_ALL,
|
||
|
|
"vasr",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,11,CPU_ALL,
|
||
|
|
"vasr",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,11,CPU_ALL,
|
||
|
|
|
||
|
|
"vsshl",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,12,CPU_ALL,
|
||
|
|
"vsshl",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,12,CPU_ALL,
|
||
|
|
"vsshl",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,12,CPU_ALL,
|
||
|
|
"vsshl",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,12,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vslsl",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,12,CPU_ALL,
|
||
|
|
"vslsl",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,12,CPU_ALL,
|
||
|
|
"vslsl",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,12,CPU_ALL,
|
||
|
|
"vslsl",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,12,CPU_ALL,
|
||
|
|
|
||
|
|
"vsasl",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,14,CPU_ALL,
|
||
|
|
"vsasl",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,14,CPU_ALL,
|
||
|
|
"vsasl",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,14,CPU_ALL,
|
||
|
|
"vsasl",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,14,CPU_ALL,
|
||
|
|
|
||
|
|
"vsasls",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,15,CPU_ALL,
|
||
|
|
"vsasls",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,15,CPU_ALL,
|
||
|
|
"vsasls",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,15,CPU_ALL,
|
||
|
|
"vsasls",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,15,CPU_ALL,
|
||
|
|
|
||
|
|
"vand",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,16,CPU_ALL,
|
||
|
|
"vand",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,16,CPU_ALL,
|
||
|
|
"vand",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,16,CPU_ALL,
|
||
|
|
"vand",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,16,CPU_ALL,
|
||
|
|
|
||
|
|
"vor",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,17,CPU_ALL,
|
||
|
|
"vor",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,17,CPU_ALL,
|
||
|
|
"vor",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,17,CPU_ALL,
|
||
|
|
"vor",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,17,CPU_ALL,
|
||
|
|
|
||
|
|
"veor",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,18,CPU_ALL,
|
||
|
|
"veor",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,18,CPU_ALL,
|
||
|
|
"veor",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,18,CPU_ALL,
|
||
|
|
"veor",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,18,CPU_ALL,
|
||
|
|
|
||
|
|
"vandn",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,19,CPU_ALL,
|
||
|
|
"vandn",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,19,CPU_ALL,
|
||
|
|
"vandn",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,19,CPU_ALL,
|
||
|
|
"vandn",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,19,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vbic",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,19,CPU_ALL,
|
||
|
|
"vbic",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,19,CPU_ALL,
|
||
|
|
"vbic",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,19,CPU_ALL,
|
||
|
|
"vbic",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,19,CPU_ALL,
|
||
|
|
|
||
|
|
"vpopcnt",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,20,CPU_ALL,
|
||
|
|
"vpopcnt",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,20,CPU_ALL,
|
||
|
|
"vpopcnt",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,20,CPU_ALL,
|
||
|
|
"vpopcnt",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,20,CPU_ALL,
|
||
|
|
|
||
|
|
"vlog2",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,21,CPU_ALL,
|
||
|
|
"vlog2",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,21,CPU_ALL,
|
||
|
|
"vlog2",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,21,CPU_ALL,
|
||
|
|
"vlog2",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,21,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vmsb",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,21,CPU_ALL,
|
||
|
|
"vmsb",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,21,CPU_ALL,
|
||
|
|
"vmsb",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,21,CPU_ALL,
|
||
|
|
"vmsb",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,21,CPU_ALL,
|
||
|
|
|
||
|
|
"vmin",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,24,CPU_ALL,
|
||
|
|
"vmin",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,24,CPU_ALL,
|
||
|
|
"vmin",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,24,CPU_ALL,
|
||
|
|
"vmin",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,24,CPU_ALL,
|
||
|
|
|
||
|
|
"vmax",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,25,CPU_ALL,
|
||
|
|
"vmax",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,25,CPU_ALL,
|
||
|
|
"vmax",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,25,CPU_ALL,
|
||
|
|
"vmax",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,25,CPU_ALL,
|
||
|
|
|
||
|
|
"vdist",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,26,CPU_ALL,
|
||
|
|
"vdist",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,26,CPU_ALL,
|
||
|
|
"vdist",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,26,CPU_ALL,
|
||
|
|
"vdist",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,26,CPU_ALL,
|
||
|
|
|
||
|
|
"vdists",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,27,CPU_ALL,
|
||
|
|
"vdists",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,27,CPU_ALL,
|
||
|
|
"vdists",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,27,CPU_ALL,
|
||
|
|
"vdists",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,27,CPU_ALL,
|
||
|
|
|
||
|
|
"vclamp",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,28,CPU_ALL,
|
||
|
|
"vclamp",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,28,CPU_ALL,
|
||
|
|
"vclamp",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,28,CPU_ALL,
|
||
|
|
"vclamp",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,28,CPU_ALL,
|
||
|
|
|
||
|
|
"vsgn",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,29,CPU_ALL,
|
||
|
|
"vsgn",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,29,CPU_ALL,
|
||
|
|
"vsgn",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,29,CPU_ALL,
|
||
|
|
"vsgn",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,29,CPU_ALL,
|
||
|
|
|
||
|
|
"vclamps",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,30,CPU_ALL,
|
||
|
|
"vclamps",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,30,CPU_ALL,
|
||
|
|
"vclamps",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,30,CPU_ALL,
|
||
|
|
"vclamps",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,30,CPU_ALL,
|
||
|
|
|
||
|
|
// TODO: test this
|
||
|
|
"vcmpge",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,31,CPU_ALL,
|
||
|
|
"vcmpge",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,31,CPU_ALL,
|
||
|
|
"vcmpge",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,31,CPU_ALL,
|
||
|
|
"vcmpge",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,31,CPU_ALL,
|
||
|
|
|
||
|
|
"vadd",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,32,CPU_ALL,
|
||
|
|
"vadd",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,32,CPU_ALL,
|
||
|
|
"vadd",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,32,CPU_ALL,
|
||
|
|
"vadd",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,32,CPU_ALL,
|
||
|
|
|
||
|
|
"vadds",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,33,CPU_ALL,
|
||
|
|
"vadds",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,33,CPU_ALL,
|
||
|
|
"vadds",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,33,CPU_ALL,
|
||
|
|
"vadds",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,33,CPU_ALL,
|
||
|
|
|
||
|
|
"vaddc",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,34,CPU_ALL,
|
||
|
|
"vaddc",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,34,CPU_ALL,
|
||
|
|
"vaddc",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,34,CPU_ALL,
|
||
|
|
"vaddc",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,34,CPU_ALL,
|
||
|
|
|
||
|
|
"vaddsc",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,35,CPU_ALL,
|
||
|
|
"vaddsc",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,35,CPU_ALL,
|
||
|
|
"vaddsc",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,35,CPU_ALL,
|
||
|
|
"vaddsc",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,35,CPU_ALL,
|
||
|
|
|
||
|
|
"vsub",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,36,CPU_ALL,
|
||
|
|
"vsub",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,36,CPU_ALL,
|
||
|
|
"vsub",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,36,CPU_ALL,
|
||
|
|
"vsub",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,36,CPU_ALL,
|
||
|
|
|
||
|
|
"vsubs",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,37,CPU_ALL,
|
||
|
|
"vsubs",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,37,CPU_ALL,
|
||
|
|
"vsubs",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,37,CPU_ALL,
|
||
|
|
"vsubs",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,37,CPU_ALL,
|
||
|
|
|
||
|
|
"vsubc",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,38,CPU_ALL,
|
||
|
|
"vsubc",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,38,CPU_ALL,
|
||
|
|
"vsubc",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,38,CPU_ALL,
|
||
|
|
"vsubc",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,38,CPU_ALL,
|
||
|
|
|
||
|
|
"vsubsc",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,39,CPU_ALL,
|
||
|
|
"vsubsc",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,39,CPU_ALL,
|
||
|
|
"vsubsc",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,39,CPU_ALL,
|
||
|
|
"vsubsc",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,39,CPU_ALL,
|
||
|
|
|
||
|
|
"vrsb",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,40,CPU_ALL,
|
||
|
|
"vrsb",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,40,CPU_ALL,
|
||
|
|
"vrsb",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,40,CPU_ALL,
|
||
|
|
"vrsb",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,40,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vrsub",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,40,CPU_ALL,
|
||
|
|
"vrsub",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,40,CPU_ALL,
|
||
|
|
"vrsub",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,40,CPU_ALL,
|
||
|
|
"vrsub",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,40,CPU_ALL,
|
||
|
|
|
||
|
|
"vrsbs",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,41,CPU_ALL,
|
||
|
|
"vrsbs",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,41,CPU_ALL,
|
||
|
|
"vrsbs",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,41,CPU_ALL,
|
||
|
|
"vrsbs",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,41,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vrsubs",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,41,CPU_ALL,
|
||
|
|
"vrsubs",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,41,CPU_ALL,
|
||
|
|
"vrsubs",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,41,CPU_ALL,
|
||
|
|
"vrsubs",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,41,CPU_ALL,
|
||
|
|
|
||
|
|
"vrsbc",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,42,CPU_ALL,
|
||
|
|
"vrsbc",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,42,CPU_ALL,
|
||
|
|
"vrsbc",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,42,CPU_ALL,
|
||
|
|
"vrsbc",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,42,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vrsubc",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,42,CPU_ALL,
|
||
|
|
"vrsubc",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,42,CPU_ALL,
|
||
|
|
"vrsubc",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,42,CPU_ALL,
|
||
|
|
"vrsubc",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,42,CPU_ALL,
|
||
|
|
|
||
|
|
"vrsbsc",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,43,CPU_ALL,
|
||
|
|
"vrsbsc",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,43,CPU_ALL,
|
||
|
|
"vrsbsc",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,43,CPU_ALL,
|
||
|
|
"vrsbsc",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,43,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vrsubsc",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,43,CPU_ALL,
|
||
|
|
"vrsubsc",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,43,CPU_ALL,
|
||
|
|
"vrsubsc",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,43,CPU_ALL,
|
||
|
|
"vrsubsc",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,43,CPU_ALL,
|
||
|
|
|
||
|
|
// Operations 48-63 do different things depending on the 'X' bit
|
||
|
|
// (equivalently, the 64 bit in the opcode)
|
||
|
|
// First, X=0
|
||
|
|
|
||
|
|
"vmul",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,48,CPU_ALL,
|
||
|
|
"vmul",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,48,CPU_ALL,
|
||
|
|
"vmul",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,48,CPU_ALL,
|
||
|
|
"vmul",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,48,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vmull",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,48,CPU_ALL,
|
||
|
|
"vmull",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,48,CPU_ALL,
|
||
|
|
"vmull",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,48,CPU_ALL,
|
||
|
|
"vmull",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,48,CPU_ALL,
|
||
|
|
|
||
|
|
"vmuls",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,49,CPU_ALL,
|
||
|
|
"vmuls",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,49,CPU_ALL,
|
||
|
|
"vmuls",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,49,CPU_ALL,
|
||
|
|
"vmuls",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,49,CPU_ALL,
|
||
|
|
// Alternate name
|
||
|
|
"vmulls",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,49,CPU_ALL,
|
||
|
|
"vmulls",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,49,CPU_ALL,
|
||
|
|
"vmulls",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,49,CPU_ALL,
|
||
|
|
"vmulls",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,49,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulmd",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,50,CPU_ALL,
|
||
|
|
"vmulmd",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,50,CPU_ALL,
|
||
|
|
"vmulmd",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,50,CPU_ALL,
|
||
|
|
"vmulmd",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,50,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulmds",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,51,CPU_ALL,
|
||
|
|
"vmulmds",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,51,CPU_ALL,
|
||
|
|
"vmulmds",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,51,CPU_ALL,
|
||
|
|
"vmulmds",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,51,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulhds",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,52,CPU_ALL,
|
||
|
|
"vmulhds",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,52,CPU_ALL,
|
||
|
|
"vmulhds",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,52,CPU_ALL,
|
||
|
|
"vmulhds",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,52,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulhdsu",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,53,CPU_ALL,
|
||
|
|
"vmulhdsu",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,53,CPU_ALL,
|
||
|
|
"vmulhdsu",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,53,CPU_ALL,
|
||
|
|
"vmulhdsu",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,53,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulhdus",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,54,CPU_ALL,
|
||
|
|
"vmulhdus",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,54,CPU_ALL,
|
||
|
|
"vmulhdus",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,54,CPU_ALL,
|
||
|
|
"vmulhdus",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,54,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulhdu",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,55,CPU_ALL,
|
||
|
|
"vmulhdu",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,55,CPU_ALL,
|
||
|
|
"vmulhdu",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,55,CPU_ALL,
|
||
|
|
"vmulhdu",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,55,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulhdrs",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,56,CPU_ALL,
|
||
|
|
"vmulhdrs",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,56,CPU_ALL,
|
||
|
|
"vmulhdrs",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,56,CPU_ALL,
|
||
|
|
"vmulhdrs",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,56,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulhdrsu",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,57,CPU_ALL,
|
||
|
|
"vmulhdrsu",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,57,CPU_ALL,
|
||
|
|
"vmulhdrsu",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,57,CPU_ALL,
|
||
|
|
"vmulhdrsu",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,57,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulhdrus",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,58,CPU_ALL,
|
||
|
|
"vmulhdrus",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,58,CPU_ALL,
|
||
|
|
"vmulhdrus",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,58,CPU_ALL,
|
||
|
|
"vmulhdrus",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,58,CPU_ALL,
|
||
|
|
|
||
|
|
"vmulhdru",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,59,CPU_ALL,
|
||
|
|
"vmulhdru",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,59,CPU_ALL,
|
||
|
|
"vmulhdru",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,59,CPU_ALL,
|
||
|
|
"vmulhdru",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,59,CPU_ALL,
|
||
|
|
|
||
|
|
// Then X=1
|
||
|
|
|
||
|
|
"vmul32s",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,52|64,CPU_ALL,
|
||
|
|
"vmul32s",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,52|64,CPU_ALL,
|
||
|
|
"vmul32s",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,52|64,CPU_ALL,
|
||
|
|
"vmul32s",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,52|64,CPU_ALL,
|
||
|
|
|
||
|
|
"vmul32su",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,53|64,CPU_ALL,
|
||
|
|
"vmul32su",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,53|64,CPU_ALL,
|
||
|
|
"vmul32su",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,53|64,CPU_ALL,
|
||
|
|
"vmul32su",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,53|64,CPU_ALL,
|
||
|
|
|
||
|
|
"vmul32us",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,54|64,CPU_ALL,
|
||
|
|
"vmul32us",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,54|64,CPU_ALL,
|
||
|
|
"vmul32us",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,54|64,CPU_ALL,
|
||
|
|
"vmul32us",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,54|64,CPU_ALL,
|
||
|
|
|
||
|
|
"vmul32u",OP_VREG,OP_VREG,OP_VREG,0,EN_VARITHR48,55|64,CPU_ALL,
|
||
|
|
"vmul32u",OP_VREGM,OP_VREGA80,OP_VREGMM,0,EN_VARITHR80,55|64,CPU_ALL,
|
||
|
|
"vmul32u",OP_VREG,OP_VREG,OP_IMM6,0,EN_VARITHI48,55|64,CPU_ALL,
|
||
|
|
"vmul32u",OP_VREGM,OP_VREGA80,OP_IMM32M,0,EN_VARITHI80,55|64,CPU_ALL,
|