588 lines
12 KiB
C
588 lines
12 KiB
C
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/* Operand description structure */
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struct powerpc_operand
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{
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int bits;
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int shift;
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uint32_t (*insert)(uint32_t,int32_t,const char **);
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uint32_t flags;
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};
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/* powerpc_operand flags */
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#define OPER_SIGNED (1) /* signed values */
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#define OPER_SIGNOPT (2) /* signed values up to 0xffff */
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#define OPER_FAKE (4) /* just reuse last read operand */
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#define OPER_PARENS (8) /* operand is in parentheses */
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#define OPER_CR (0x10) /* CR field */
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#define OPER_GPR (0x20) /* GPR field */
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#define OPER_FPR (0x40) /* FPR field */
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#define OPER_RELATIVE (0x80) /* relative branch displacement */
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#define OPER_ABSOLUTE (0x100) /* absolute branch address */
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#define OPER_OPTIONAL (0x200) /* optional, zero if omitted */
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#define OPER_NEXT (0x400) /* hack for rotate instructions */
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#define OPER_NEGATIVE (0x800) /* range check on negative value */
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#define OPER_VR (0x1000) /* Altivec register field */
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/* Operand types. */
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enum {
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UNUSED,BA,BAT,BB,BBA,BD,BDA,BDM,BDMA,BDP,BDPA,BF,OBF,BFA,BI,BO,BOE,
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BT,CR,D,DS,E,FL1,FL2,FLM,FRA,FRB,FRC,FRS,FXM,L,LEV,LI,LIA,MB,ME,
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MBE,MBE_,MB6,NB,NSI,RA,RAL,RAM,RAS,RB,RBS,RS,SH,SH6,SI,SISIGNOPT,
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SPR,SPRBAT,SPRG,SR,SV,TBR,TO,U,UI,VA,VB,VC,VD,SIMM,UIMM,SHB,
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SLWI,SRWI,EXTLWI,EXTRWI,EXTWIB,INSLWI,INSRWI,ROTRWI,CLRRWI,CLRLSL,
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STRM,AT,LS,RSOPT,RAOPT,RBOPT,CT,SHO,CRFS,EVUIMM_2,EVUIMM_4,EVUIMM_8
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};
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#define FRT FRS
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#define ME6 MB6
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#define RT RS
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#define RTOPT RSOPT
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#define VS VD
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#define CRB MB
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#define PMR SPR
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#define TMR SPR
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#define CRFD BF
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#define EVUIMM SH
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#define NEXT (-1) /* use operand_type+1 for next operand */
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/* The functions used to insert complex operands. */
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static uint32_t insert_bat(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | (((insn >> 21) & 0x1f) << 16);
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}
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static uint32_t insert_bba(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | (((insn >> 16) & 0x1f) << 11);
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}
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static uint32_t insert_bd(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | (value & 0xfffc);
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}
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static uint32_t insert_bdm(uint32_t insn,int32_t value,const char **errmsg)
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{
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if ((value & 0x8000) != 0)
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insn |= 1 << 21;
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return insn | (value & 0xfffc);
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}
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static uint32_t insert_bdp(uint32_t insn,int32_t value,const char **errmsg)
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{
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if ((value & 0x8000) == 0)
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insn |= 1 << 21;
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return insn | (value & 0xfffc);
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}
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static int valid_bo(int32_t value)
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{
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switch (value & 0x14) {
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default:
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case 0:
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return 1;
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case 0x4:
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return (value & 0x2) == 0;
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case 0x10:
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return (value & 0x8) == 0;
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case 0x14:
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return value == 0x14;
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}
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}
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static uint32_t insert_bo(uint32_t insn,int32_t value,const char **errmsg)
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{
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if (!valid_bo (value))
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*errmsg = "invalid conditional option";
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return insn | ((value & 0x1f) << 21);
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}
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static uint32_t insert_boe(uint32_t insn,int32_t value,const char **errmsg)
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{
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if (!valid_bo (value))
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*errmsg = "invalid conditional option";
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else if ((value & 1) != 0)
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*errmsg = "attempt to set y bit when using + or - modifier";
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return insn | ((value & 0x1f) << 21);
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}
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static uint32_t insert_ds(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | (value & 0xfffc);
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}
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static uint32_t insert_li(uint32_t insn,int32_t value,const char **errmsg)
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{
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if ((value & 3) != 0)
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*errmsg = "ignoring least significant bits in branch offset";
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return insn | (value & 0x3fffffc);
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}
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static uint32_t insert_mbe(uint32_t insn,int32_t value,const char **errmsg)
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{
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uint32_t uval, mask;
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int mb, me, mx, count, last;
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uval = value;
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if (uval == 0) {
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*errmsg = "illegal bitmask";
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return insn;
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}
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mb = 0;
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me = 32;
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if ((uval & 1) != 0)
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last = 1;
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else
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last = 0;
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count = 0;
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for (mx = 0, mask = (int32_t) 1 << 31; mx < 32; ++mx, mask >>= 1) {
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if ((uval & mask) && !last) {
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++count;
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mb = mx;
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last = 1;
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}
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else if (!(uval & mask) && last) {
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++count;
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me = mx;
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last = 0;
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}
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}
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if (me == 0)
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me = 32;
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if (count != 2 && (count != 0 || ! last)) {
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*errmsg = "illegal bitmask";
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}
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return insn | (mb << 6) | ((me - 1) << 1);
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}
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static uint32_t insert_mb6(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | ((value & 0x1f) << 6) | (value & 0x20);
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}
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static uint32_t insert_nb(uint32_t insn,int32_t value,const char **errmsg)
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{
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if (value < 0 || value > 32)
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*errmsg = "value out of range";
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if (value == 32)
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value = 0;
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return insn | ((value & 0x1f) << 11);
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}
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static uint32_t insert_nsi(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | ((- value) & 0xffff);
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}
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static uint32_t insert_ral(uint32_t insn,int32_t value,const char **errmsg)
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{
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if (value == 0
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|| (uint32_t) value == ((insn >> 21) & 0x1f))
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*errmsg = "invalid register operand when updating";
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return insn | ((value & 0x1f) << 16);
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}
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static uint32_t insert_ram(uint32_t insn,int32_t value,const char **errmsg)
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{
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if ((uint32_t) value >= ((insn >> 21) & 0x1f))
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*errmsg = "index register in load range";
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return insn | ((value & 0x1f) << 16);
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}
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static uint32_t insert_ras(uint32_t insn,int32_t value,const char **errmsg)
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{
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if (value == 0)
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*errmsg = "invalid register operand when updating";
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return insn | ((value & 0x1f) << 16);
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}
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static uint32_t insert_rbs(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | (((insn >> 21) & 0x1f) << 11);
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}
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static uint32_t insert_sh6(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
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}
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static uint32_t insert_spr(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
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}
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static uint32_t insert_sprg(uint32_t insn,int32_t value,const char **errmsg)
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{
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/* @@@ only BOOKE, VLE and 405 have 8 SPRGs */
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if (value & ~7)
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*errmsg = "illegal SPRG number";
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if ((insn & 0x100)!=0 || value<=3)
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value |= 0x10; /* mfsprg 4..7 use SPR260..263 */
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return insn | ((value & 17) << 16);
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}
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static uint32_t insert_tbr(uint32_t insn,int32_t value,const char **errmsg)
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{
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if (value == 0)
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value = 268;
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return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
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}
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static uint32_t insert_slwi(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | ((value&0x1f)<<11) | ((31-(value&0x1f))<<1);
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}
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static uint32_t insert_srwi(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | (((32-value)&0x1f)<<11) | ((value&0x1f)<<6) | (31<<1);
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}
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static uint32_t insert_extlwi(uint32_t insn,int32_t value,const char **errmsg)
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{
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if (value<1 || value>32)
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*errmsg = "value out of range (1-32)";
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return insn | (((value-1)&0x1f)<<1);
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}
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static uint32_t insert_extrwi(uint32_t insn,int32_t value,const char **errmsg)
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{
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if (value<1 || value>32)
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*errmsg = "value out of range (1-32)";
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return insn | ((value&0x1f)<<11) | (((32-value)&0x1f)<<6) | (31<<1);
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}
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static uint32_t insert_extwib(uint32_t insn,int32_t value,const char **errmsg)
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{
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value += (insn>>11) & 0x1f;
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if (value > 32)
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*errmsg = "sum of last two operands out of range (0-32)";
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return (insn&~0xf800) | ((value&0x1f)<<11);
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}
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static uint32_t insert_inslwi(uint32_t insn,int32_t value,const char **errmsg)
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{
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int32_t n = ((insn>>1) & 0x1f) + 1;
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if (value+n > 32)
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*errmsg = "sum of last two operands out of range (1-32)";
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return (insn&~0xfffe) | (((32-value)&0x1f)<<11) | ((value&0x1f)<<6)
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| ((((value+n)-1)&0x1f)<<1);
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}
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static uint32_t insert_insrwi(uint32_t insn,int32_t value,const char **errmsg)
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{
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int32_t n = ((insn>>1) & 0x1f) + 1;
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if (value+n > 32)
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*errmsg = "sum of last two operands out of range (1-32)";
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return (insn&~0xfffe) | (((32-(value+n))&0x1f)<<11) | ((value&0x1f)<<6)
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| ((((value+n)-1)&0x1f)<<1);
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}
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static uint32_t insert_rotrwi(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | (((32-value)&0x1f)<<11);
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}
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static uint32_t insert_clrrwi(uint32_t insn,int32_t value,const char **errmsg)
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{
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return insn | (((31-value)&0x1f)<<1);
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}
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static uint32_t insert_clrlslwi(uint32_t insn,int32_t value,const char **errmsg)
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{
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int32_t b = (insn>>6) & 0x1f;
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if (value > b)
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*errmsg = "n (4th oper) must be less or equal to b (3rd oper)";
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return (insn&~0x7c0) | ((value&0x1f)<<11) | (((b-value)&0x1f)<<6)
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| (((31-value)&0x1f)<<1);
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}
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static uint32_t insert_ls(uint32_t insn,int32_t value,const char **errmsg)
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{
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/* @@@ check for POWER4 */
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return insn | ((value&3)<<21);
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}
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/* The operands table.
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The fields are: bits, shift, insert, flags. */
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const struct powerpc_operand powerpc_operands[] =
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{
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/* UNUSED */
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{ 0, 0, 0, 0 },
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/* BA */
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{ 5, 16, 0, OPER_CR },
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/* BAT */
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{ 5, 16, insert_bat, OPER_FAKE },
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/* BB */
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{ 5, 11, 0, OPER_CR },
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/* BBA */
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{ 5, 11, insert_bba, OPER_FAKE },
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/* BD */
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{ 16, 0, insert_bd, OPER_RELATIVE | OPER_SIGNED },
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/* BDA */
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{ 16, 0, insert_bd, OPER_ABSOLUTE | OPER_SIGNED },
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/* BDM */
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{ 16, 0, insert_bdm, OPER_RELATIVE | OPER_SIGNED },
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/* BDMA */
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{ 16, 0, insert_bdm, OPER_ABSOLUTE | OPER_SIGNED },
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/* BDP */
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{ 16, 0, insert_bdp, OPER_RELATIVE | OPER_SIGNED },
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||
|
|
/* BDPA */
|
||
|
|
{ 16, 0, insert_bdp, OPER_ABSOLUTE | OPER_SIGNED },
|
||
|
|
|
||
|
|
/* BF */
|
||
|
|
{ 3, 23, 0, OPER_CR },
|
||
|
|
|
||
|
|
/* OBF */
|
||
|
|
{ 3, 23, 0, OPER_CR | OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* BFA */
|
||
|
|
{ 3, 18, 0, OPER_CR },
|
||
|
|
|
||
|
|
/* BI */
|
||
|
|
{ 5, 16, 0, OPER_CR },
|
||
|
|
|
||
|
|
/* BO */
|
||
|
|
{ 5, 21, insert_bo, 0 },
|
||
|
|
|
||
|
|
/* BOE */
|
||
|
|
{ 5, 21, insert_boe, 0 },
|
||
|
|
|
||
|
|
/* BT */
|
||
|
|
{ 5, 21, 0, OPER_CR },
|
||
|
|
|
||
|
|
/* CR */
|
||
|
|
{ 3, 18, 0, OPER_CR | OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* D */
|
||
|
|
{ 16, 0, 0, OPER_PARENS | OPER_SIGNED },
|
||
|
|
|
||
|
|
/* DS */
|
||
|
|
{ 16, 0, insert_ds, OPER_PARENS | OPER_SIGNED },
|
||
|
|
|
||
|
|
/* E */
|
||
|
|
{ 1, 15, 0, 0 },
|
||
|
|
|
||
|
|
/* FL1 */
|
||
|
|
{ 4, 12, 0, 0 },
|
||
|
|
|
||
|
|
/* FL2 */
|
||
|
|
{ 3, 2, 0, 0 },
|
||
|
|
|
||
|
|
/* FLM */
|
||
|
|
{ 8, 17, 0, 0 },
|
||
|
|
|
||
|
|
/* FRA */
|
||
|
|
{ 5, 16, 0, OPER_FPR },
|
||
|
|
|
||
|
|
/* FRB */
|
||
|
|
{ 5, 11, 0, OPER_FPR },
|
||
|
|
|
||
|
|
/* FRC */
|
||
|
|
{ 5, 6, 0, OPER_FPR },
|
||
|
|
|
||
|
|
/* FRS */
|
||
|
|
{ 5, 21, 0, OPER_FPR },
|
||
|
|
|
||
|
|
/* FXM */
|
||
|
|
{ 8, 12, 0, 0 },
|
||
|
|
|
||
|
|
/* L */
|
||
|
|
{ 1, 21, 0, OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* LEV */
|
||
|
|
{ 7, 5, 0, 0 },
|
||
|
|
|
||
|
|
/* LI */
|
||
|
|
{ 26, 0, insert_li, OPER_RELATIVE | OPER_SIGNED },
|
||
|
|
|
||
|
|
/* LIA */
|
||
|
|
{ 26, 0, insert_li, OPER_ABSOLUTE | OPER_SIGNED },
|
||
|
|
|
||
|
|
/* MB */
|
||
|
|
{ 5, 6, 0, 0 },
|
||
|
|
|
||
|
|
/* ME */
|
||
|
|
{ 5, 1, 0, 0 },
|
||
|
|
|
||
|
|
/* MBE */
|
||
|
|
{ 5, 6, 0, OPER_OPTIONAL | OPER_NEXT },
|
||
|
|
/* MBE_ (NEXT) */
|
||
|
|
{ 31, 1, insert_mbe, 0 },
|
||
|
|
|
||
|
|
/* MB6 */
|
||
|
|
{ 6, 5, insert_mb6, 0 },
|
||
|
|
|
||
|
|
/* NB */
|
||
|
|
{ 6, 11, insert_nb, 0 },
|
||
|
|
|
||
|
|
/* NSI */
|
||
|
|
{ 16, 0, insert_nsi, OPER_NEGATIVE | OPER_SIGNED },
|
||
|
|
|
||
|
|
/* RA */
|
||
|
|
{ 5, 16, 0, OPER_GPR },
|
||
|
|
|
||
|
|
/* RAL */
|
||
|
|
{ 5, 16, insert_ral, OPER_GPR },
|
||
|
|
|
||
|
|
/* RAM */
|
||
|
|
{ 5, 16, insert_ram, OPER_GPR },
|
||
|
|
|
||
|
|
/* RAS */
|
||
|
|
{ 5, 16, insert_ras, OPER_GPR },
|
||
|
|
|
||
|
|
/* RB */
|
||
|
|
{ 5, 11, 0, OPER_GPR },
|
||
|
|
|
||
|
|
/* RBS */
|
||
|
|
{ 5, 1, insert_rbs, OPER_FAKE },
|
||
|
|
|
||
|
|
/* RS */
|
||
|
|
{ 5, 21, 0, OPER_GPR },
|
||
|
|
|
||
|
|
/* SH */
|
||
|
|
{ 5, 11, 0, 0 },
|
||
|
|
|
||
|
|
/* SH6 */
|
||
|
|
{ 6, 1, insert_sh6, 0 },
|
||
|
|
|
||
|
|
/* SI */
|
||
|
|
{ 16, 0, 0, OPER_SIGNED },
|
||
|
|
|
||
|
|
/* SISIGNOPT */
|
||
|
|
{ 16, 0, 0, OPER_SIGNED | OPER_SIGNOPT },
|
||
|
|
|
||
|
|
/* SPR */
|
||
|
|
{ 10, 11, insert_spr, 0 },
|
||
|
|
|
||
|
|
/* SPRBAT */
|
||
|
|
{ 2, 17, 0, 0 },
|
||
|
|
|
||
|
|
/* SPRG */
|
||
|
|
{ 3, 16, insert_sprg, 0 },
|
||
|
|
|
||
|
|
/* SR */
|
||
|
|
{ 4, 16, 0, 0 },
|
||
|
|
|
||
|
|
/* SV */
|
||
|
|
{ 14, 2, 0, 0 },
|
||
|
|
|
||
|
|
/* TBR */
|
||
|
|
{ 10, 11, insert_tbr, OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* TO */
|
||
|
|
{ 5, 21, 0, 0 },
|
||
|
|
|
||
|
|
/* U */
|
||
|
|
{ 4, 12, 0, 0 },
|
||
|
|
|
||
|
|
/* UI */
|
||
|
|
{ 16, 0, 0, 0 },
|
||
|
|
|
||
|
|
/* VA */
|
||
|
|
{ 5, 16, 0, OPER_VR },
|
||
|
|
|
||
|
|
/* VB */
|
||
|
|
{ 5, 11, 0, OPER_VR },
|
||
|
|
|
||
|
|
/* VC */
|
||
|
|
{ 5, 6, 0, OPER_VR },
|
||
|
|
|
||
|
|
/* VD */
|
||
|
|
{ 5, 21, 0, OPER_VR },
|
||
|
|
|
||
|
|
/* SIMM */
|
||
|
|
{ 5, 16, 0, OPER_SIGNED},
|
||
|
|
|
||
|
|
/* UIMM */
|
||
|
|
{ 5, 16, 0, 0 },
|
||
|
|
|
||
|
|
/* SHB */
|
||
|
|
{ 4, 6, 0, 0 },
|
||
|
|
|
||
|
|
/* SLWI */
|
||
|
|
{ 5, 11, insert_slwi, 0 },
|
||
|
|
|
||
|
|
/* SRWI */
|
||
|
|
{ 5, 11, insert_srwi, 0 },
|
||
|
|
|
||
|
|
/* EXTLWI */
|
||
|
|
{ 31, 1, insert_extlwi, 0 },
|
||
|
|
|
||
|
|
/* EXTRWI */
|
||
|
|
{ 31, 1, insert_extrwi, 0 },
|
||
|
|
|
||
|
|
/* EXTWIB */
|
||
|
|
{ 5, 11, insert_extwib, 0 },
|
||
|
|
|
||
|
|
/* INSLWI */
|
||
|
|
{ 5, 11, insert_inslwi, 0 },
|
||
|
|
|
||
|
|
/* INSRWI */
|
||
|
|
{ 5, 11, insert_insrwi, 0 },
|
||
|
|
|
||
|
|
/* ROTRWI */
|
||
|
|
{ 5, 11, insert_rotrwi, 0 },
|
||
|
|
|
||
|
|
/* CLRRWI */
|
||
|
|
{ 5, 1, insert_clrrwi, 0 },
|
||
|
|
|
||
|
|
/* CLRLSL */
|
||
|
|
{ 5, 11, insert_clrlslwi, 0 },
|
||
|
|
|
||
|
|
/* STRM */
|
||
|
|
{ 2, 21, 0, 0 },
|
||
|
|
|
||
|
|
/* AT */
|
||
|
|
{ 1, 25, 0, OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* LS */
|
||
|
|
{ 2, 21, insert_ls, OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* RSOPT */
|
||
|
|
{ 5, 21, 0, OPER_GPR | OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* RAOPT */
|
||
|
|
{ 5, 16, 0, OPER_GPR | OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* RBOPT */
|
||
|
|
{ 5, 11, 0, OPER_GPR | OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* CT */
|
||
|
|
{ 5, 21, 0, OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* SHO */
|
||
|
|
{ 5, 11, 0, OPER_OPTIONAL },
|
||
|
|
|
||
|
|
/* CRFS */
|
||
|
|
{ 3, 0, 0, OPER_CR },
|
||
|
|
|
||
|
|
/* EVUIMM_2 */
|
||
|
|
{ 5, 10, 0, OPER_PARENS },
|
||
|
|
|
||
|
|
/* EVUIMM_4 */
|
||
|
|
{ 5, 9, 0, OPER_PARENS },
|
||
|
|
|
||
|
|
/* EVUIMM_8 */
|
||
|
|
{ 5, 8, 0, OPER_PARENS },
|
||
|
|
};
|